News

November 2017

Dr. Bakir appointed as Editor-in-Chief for IEEE CPMT journal

February 2017

Dr. Bakir received the 2016 Class of Course Survey Teaching Effectiveness Award

January 2017

Hanju and Xuchen received Best Oral Session Paper Award at ECTC

Nov 2016

Reza received Outstanding Abstract Achievement Award at American Society of Hematology

September 2016

Will received Best in Session Award at SRC TECHCON

May 2016

Reza received Best Poster Award at Annual User Science and Engineering Review from The Institute for Electronics and Nanotechnology (IEN)

April 2016

Joe Gonzalez awarded Goizueta Foundation Fellowship

March 2016

Muneeb Zia and Paul Jo received Best Team Award in NSF I-Corps in 2016 Winter Cohort

February 2016

Joe Gonzalez awarded GEM Fellowship

December 2015

Muneeb Zia and Paul Jo won NSF I-Corps Grant for 2016 Winter Cohort

November 2015

Microfluidic cooled FPGA featured in IEEE Spectrum.

November 2015

Reza Abbaspour won best student paper award at GIT 2015

October 2015

Microfluidic cooled FPGA featured in Georgia Tech news.

June 2015

M. Bakir was appointed as IEEE CPMT distinguished lecturer.

March 2015

James Yang and Chaoqi Zhang received the 2014 Best TCPMT journal paper award for Advanced Packaging.

Publications & Patents


Books and Book Chapters
1.M. Zia, C.Wan, Y. Zhang and M.S. Bakir, (2016). Electrical and photonic off-chip interconnection and system integration. In Tolga Tekin, Nikos Pleros, Richard Pitwon, and Andreas Hakansson (Ed.), Optical Interconnects for Data Centers (1st ed., p265-p286). Woodhead Publishing
1.H. S. Yang, P. Thadesar, C. Zhang, M.S. Bakir, (2013). Mechanically Flexible Interconnects and TSVs: Applications in CMOS/MEMS Integration. In L. A. Francis and K. Iniewski (Ed.), Novel Advances in Microsystems Technologies and Their Applications (1st ed., p45-p68). FL, USA: CRC Pres
2.H. S. Yang, P. Thadesar, C. Zhang, M.S. Bakir, (2013). Mechanically Flexible Interconnects and TSVs: Applications in CMOS/MEMS Integration. In V. Choudhary and K. Iniewski (Ed.), MEMS: Fundamental Technology and Applications (1st ed., p111-p130). FL, USA: CRC Press
3.M. Bakir, G. Huang, and B. Dang, "3D Integration: Limits and Opportunities," in Coupled Data Techniques, R. Ho and R. Drost (Eds.), Chapter 2, Springer, 2010.
4.G. Huang, K. Shakeri, A. Naeemi, M. Bakir, and J. Meindl, "On-Chip Power Supply Noise Modeling and Chip/Package Co-Design of Gigascale and 3D Integrations," in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl (Eds.), Artech House 2009.
5.B. Dang, M. Bakir, D. Sekar, C. King, and J. Meindl, "Single and 3D Chip Cooling using Microchannels and Fluidic I/Os," in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl (Eds.), Artech House 2009.
6.M. Bakir and J. Meindl, "Revolutionary Silicon Ancillary Technologies for the Next Era of Gigascale Integration," in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl (Eds.), Artech House 2009.
7.M. Bakir and J. Meindl (Eds.), Integrated Interconnect Technologies for 3D Nanoelectronic Systems, Artech House, 2009. (16 chapters; 550-pages)
8.M. Bakir, "Nanoimprint Lithography for Semiconductor and Interconnect Technologies," in NanoTechnology: An Open Text, S. Campbell (Ed.), NSF NNIN 2007.
Refereed Journal Publications
1.T. E. Sarvey, Y. Hu, C. E. Green, P. A. Kottke, D. C. Woodrum, Y. K. Joshi, A. G. Fedorov, S. K. Sitaraman, and M. S. Bakir, "Integrated circuit cooling using heterogeneous micropin-fin arrays for nonuniform power maps," IEEE Trans. on Components, Packaging and Manufacturing Technology, 2017. (Accepted)
2.T. E. Sarvey, Y. Zhang, C. Cheung, R. Gutala. A. Rahman, A. Dasu, and M. S. Bakir, "Monolithic integration of a micropin-fin heat sink in a 28 nm FPGA," IEEE Trans. on Components, Packaging and Manufacturing Technology, 2017. (Accepted)
3.J. C. Ciciliano, R. Abbaspour, J. Woodall, C. Wu, M. S. Bakir, and W. A. Lam, "Probing blood cell mechanics of hematologic processes at the single micron level," Lab. Chip, vol. 17, no. 22, pp. 3804-3816, Nov. 2017.
4.C. Wan, T. K. Gaylord, and M. S. Bakir, "Circular waveguide grating-via-grating for interlayer coupling," IEEE Photonics Technology Letters, vol. 29, no. 21, pp. 1776-1779, Nov. 2017.
5.Y. Zhang, T. E. Sarvey, and M. S. Bakir, "Thermal evaluation of 2.5-D integration using bridge-chip technology challenges and opportunities", IEEE Transactions on Components, Packaging and Manufacturing Technology,vol. 7, no. 7, pp. 1101 - 1110, July 2017.
6.P. K. Jo, M. Zia, J. L. Gonzalez, H. Oh, and M. S. Bakir, "Design, fabrication, and characterization of dense compressible microinterconnects,"IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 7, no. 7, pp. 1003-1010, May. 2017.
7.H. Oh, G. May, and M. Bakir, "Heterogeneous integrated microsystems with non-traditional through-silicon via technologies," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 7, no. 4, pp. 502-510, Mar. 2017.
8.Y. Zhang, L. Zheng, M. S. Bakir, "Integrated thermal and power delivery network co-simulation framework for single-die and multi-die assemblies", IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 7, no. 3, pp. 434-443, Feb. 2017.
9.X. Zhang, P. K. Jo, M. Zia, G. May, and M. S. Bakir, "Heterogeneous interconnect stitching technology with compressible microinterconnects for dense multi-die integration," IEEE Electron Device Letters, vol. 38, no. 2, pp. 255-257, Feb. 2017.
10.C. Zhang, H. S. Yang, and M. S. Bakir, "A double-lithography and double-reflow process and application to multi-pitch multi-height mechanical flexible interconnects," Journal of Micromechanics and Microengineering, vol. 27, no. 2, pp. 025014-1-025014-6, Jan. 2017.
11.R. Abbaspour, D. K. Brown, and M. S. Bakir, "Fabrication and electrical characterization of sub-micron diameter through-silicon via for heterogeneous three-dimensional integrated circuits," Journal of Micromechanics and Microengineering, vol. 27, no. 2, pp. 025011-1-025011-8, Jan. 2017.
12.J. Ciciliano, R. Abbaspour, C. Wu, M. S. Bakir, and W. A. Lam, "A microengineered matrix to decouple the biophysical and biochemical mechanisms of blood cell interactions with thrombi and vascular wall matrices," Blood Journal by American Society of Hematology, vol. 128, no. 22, p. 555, Dec. 2016.
13.C. Wan, T. K. Gaylord, and M. S. Bakir, "Rigorous coupled-wave analysis equivalent-index-slab method for analyzing 3D angular misalignment in interlayer grating couplers," Applied Optics, vol. 55, no.35, pp. 10006-10015, Dec. 2016.
14.M. Zia, T. Chi, J. Park, A. Su, J. L. Gonzalez, P. K. Jo, M. P. Styczynski, H. Wang, and M. S. Bakir, "A 3D integrated electronic microplate platform for lowcost repeatable biosensing applications," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 6, no. 12, pp. 1827-1833, Dec. 2016.
15.C. Zhang, H. S. Yang, H. D. Thacker, I. Shubin, J. E. Cunningham, and M. S. Bakir, "Mechanically flexible interconnects with contact tip for rematable heterogeneous system integration," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 6, no. 11, pp. 1587-1594, Oct. 2016.
16.C. Wan, T. K. Gaylord, and M. S. Bakir, "Grating design for interlayer optical interconnection of in-plane waveguides," Applied Optics, vol. 55, no.10, pp. 2601-2610, Oct. 2016.
17.C. Wan, T. K. Gaylord, and M. S. Bakir, "RCWA-EIS method for interlayer grating coupling," Applied Optics, vol. 55, no. 22, pp. 5900-5908, Aug. 2016.
18.P. Thadesar, X. Gu, R. Alapati and M. S. Bakir, "TSVs: Drivers, performance and innovations (Invited)," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 6, no. 3, pp. 455-463, July 2016.
19.X. Liu, P. Thadesar, C. Taylor, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "Experimental stress characterization and numerical simulation for copper pumping analysis of through silicon vias (Invited)," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 6, no. 7, pp. 993-999, July 2016.
20.X. Zhang, V. Kumar, H. Oh, L. Zheng, G. May, A. Naeemi, and M. S. Bakir, "Impact of on-chip interconnect on the performance of 3D integrated circuits with through silicon vias Part II," IEEE Trans. Electron Devices, vol. 63, no. 6, pp. 2510-2516, June 2016.
21.V. Kumar, H. Oh, X. Zhang, L. Zheng, M. S. Bakir, and A. Naeemi, "Impact of on-chip interconnect on the performance of 3D integrated circuits with through silicon vias Part I," IEEE Trans. Electron Devices, vol. 63, no. 6, pp. 2503-2509, June 2016.
22.M. Zia, C. Zhang, H.S. Yang, L. Zheng and Muhannad Bakir, "Chip-to-chip interconnect integration technologies," IEICE Electron. Express, vol. 13, no. 6, pp. 1-16, Mar. 2016.
23.P. Thadesar and M. S. Bakir, "Fabrication and characterization of polymer-enhanced TSVs, inductors and antennas for mixed-signal silicon interposer platforms," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 6, no. 3, pp. 455-463, Mar. 2016.
24.L. Zheng, Y. Zhang, and M. Bakir, "Power supply noise full-chip time domain numerical modeling, simulation, and analysis for single and stacked ICs," IEEE Trans. Electron Devices, vol. 63, no. 3, pp. 1225-1231, Mar. 2016.
25.X. Zhang, X. Han, T. E. Sarvey, C. E. Green, P. A. Kottke, A. G. Fedorov, Y. Joshi, and M. S. Bakir, "3D IC with embedded microfluidic cooling technology, thermal performance, and electrical implications," ASME Journal of Electronic Packaging, vol. 138, pp. 1-6, Mar. 2016.
26.H. Oh, G. May, and M. Bakir, "Analysis of signal propagation through TSVs within distilled water for liquid-cooled microsystems," IEEE Trans. Electron Devices, vol. 63, no. 3, pp. 1176-1181, Mar. 2016.
27.H. Oh, P. A. Thadesar, G. S. May, and M. S. Bakir, "Low-Loss Air-Isolated Through-Silicon Vias for Silicon Interposers," IEEE Microw. Wirel. Components Lett., vol. 26, no. 3, pp. 168-170, Mar. 2016.
28.H. S. Yang, C. Zhang, and M. S. Bakir, "A Self-aligning flip-chip assembly method using sacrificial positive self-alignment structures," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 6, no. 3, pp. 471-477, Feb. 2016.
29.W. Wahby, L. Zheng, Y. Zhang, M. S. Bakir, "A simulation tool for rapid investigation of trends in 3DIC performance and power consumption," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no. 2, pp. 192-199, Feb. 2016.
30.C. Green, P. Kottke, X. Han, C. Woodrum, T. E. Sarvey, P. Asrar, X. Zhang, Y. Joshi, A. Fedorov, S. Sitaraman, M. S. Bakir, "A review of two-phase forced cooling in three-dimensional stacked electronics: technology integration," ASME Journal of Electronic Packagin, vol 137, pp. 1-9, Dec. 2015.
31.Y. Zhang, Y. Zhang, T. E. Sarvey, C. Zhang, M. Zia, M. S. Bakir, "Thermal isolation using air gap and mechanically flexible interconnects for heterogeneous 3D ICs," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 6. no. 1, pp. 31-39, Dec. 2015.
32.H. Oh, Y. Zhang, L. Zheng, G. S. May, and M. S. Bakir, "Fabrication and characterization of electrical interconnects and microfluidic cooling for 3D ICs with silicon interposer," Heat Transf. Eng., vol. 7632, pp. 1-41, Dec. 2015 (Invited).
33.L. Zheng, Y. Zhang, and M. Bakir, "A Silicon interposer platform utilizing microfluidic cooling for high-performance computing systems," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 5, pp. 1379-1386, Oct. 2015.
34.H. Oh, J. M. Gu, S. J. Hong, G. S. May, and M. S. Bakir, "High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems," Microelectronic Engineering, vol. 142, pp. 30-35, July 2015.
35.Y. Zhang, Y. Zhang, M. S. Bakir, "Thermal design and constraints for heterogeneous integrated chip stacks and isolation technology using air gap and thermal bridge," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol.4, no.12, pp.1914-1924, Dec. 2014.
36.H. S. Yang, C. Zhang and M. Bakir, "Self-aligned silicon interposer tiles and silicon bridges using positive self-alignment structures and rematable mechanically flexible interconnects",IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 4, no. 11, pp. 1760-1768, Nov. 2014.
37.H. S. Yang, C. Zhang and M. Bakir, "Self-aligning silicon interposer tiles and silicon bridges for large nanophotonics enabled systems",Electronics Letters, vol. 50, no. 20, pp. 1475-1477, Sep. 2014.
38.X. Liu, P. Thadesar, C. Taylor, H. Oh, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "In-situ microscale through-silicon via strain measurements by synchrotron x-ray microdiffraction exploring the physics behind data interpretation," Applied Physics Letters, vol.105, no.11, p.112109, Sep. 2014.
39.V. Kumar, R. Sharma, E. Uzunlar, L. Zheng, R. Bashirullah, P. Kohl, M. S. Bakir, and A. Naeemi, "Airgap interconnects: modeling, optimization, and benchmarking for backplane, PCB, and interposer applications," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol.4, no.8, pp.1335-1346, Aug. 2014.
40.J. M. Gu, P. Thadesar, A. Dembla, M. S. Bakir, G. S. May and S. J. Hong "Endpoint detection in low open area TSV fabrication using optical emission spectroscopy," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 4, no. 7, pp. 1251-1260, July 2014.
41.L. Zheng, Y. Zhang, and M. Bakir, "Novel electrical and fluidic microbumps for silicon interposer and 3D-ICs," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 4, no. 5, pp. 777-785, May 2014.
42.C. Zhang, H. S. Yang and M. Bakir, "Mechanically flexible interconnects (MFIs) with highly scalable pitch," Journal of Micromechanics and Microengineering, vol. 24, no. 5, pp. 055024-1-055024-8, May 2014.
43.Y. Zhang, L. Zheng, and M. S. Bakir, "3-D stacked tier-specific microfluidic cooling for heterogeneous 3-D ICs," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 3, no. 11, pp. 1811-1819, Nov. 2013.
44.Y. Zhang, A. Dembla, and M. S. Bakir, "Silicon micropin-fin heat sink with integrated TSVs for 3-D ICs: trade-off analysis and experimental testing," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 3, no. 11, pp. 1842-1850, Nov. 2013.
45.C. Zhang, H. S. Yang and M. Bakir, "Highly elastic gold passivated mechanically flexible interconnects," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 3, no. 10, pp. 1632-1639, Oct. 2013.
46.X. Liu, P. Thadesar, C. Taylor, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "Dimension and liner dependent thermomechanical strain characterization of through-silicon vias using synchrotron x-ray diffraction," Journal of Applied Physics, vol. 114, no. 6, pp. 064908-1-064908-7, Aug. 2013.
47.X. Liu, P. Thadesar, C. Taylor, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "Thermomechanical strain measurements by synchrotron x-ray diffraction and data interpretation for through-silicon vias," Applied Physics Letters , vol. 103, no. 2, pp. 022107-1-022107-5, July 2013.
48.P. Thadesar and M. Bakir, "Novel photo-defined polymer-enhanced through-silicon vias for silicon interposers," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 3, no. 7, pp. 1130-1137, July 2013.
49.Y. Zhang and M. S. Bakir, "Independent interlayer microfluidic cooling for heterogeneous 3D IC applications," Electronics Letters, vol. 49, no. 6, pp. 404-406, Mar. 2013.
50.P. Thadesar and M. Bakir, "Novel photodefined polymer-embedded vias for silicon interposers," Journal of Micromechanics and Microengineering, vol. 23, no. 3, pp. 035003-1-035003-6, Mar. 2013.
51.G. Huang, M. Bakir, A. Naeemi, and J. Meindl, "Power delivery for 3-D chip stacks: physical modeling and design implication," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol. 2, no. 5, pp. 852-859, May 2012.
52.H. S. Yang, M. S. Bakir, "Design, fabrication, and characterization of freestanding mechanically flexible interconnects using curved sacrificial layer," IEEE Trans. on Components, Packaging and Manufacturing Technology, vol.2, no.4, pp.561-568, Apr. 2012
53.H. S. Yang, R. Ravindran, C. Zhang, P. Modarres, and M. Bakir, "Enabling technologies for 3D stacking of disposable electronic biosensor and CMOS Chips," Future Fab International, pp. 80-85, Oct. 2011. (invited)
54.B. Dang, M. Bakir, D. Sekar, and J. Meindl, "Single and 3D chip cooling using microchannels and microfluidic chip input/output (I/O) interconnects," IEEE Trans. Adv. Packaging, vol. 3, no. 1, pp. 79-87, Feb. 2010.
55.J.-H Lai, H. S. Yang, H. Chen, C. King, J. Zaveri, R. Ravindran, and M. Bakir, "A 'mesh' seed layer for improved through-silicon-via fabrication," Journal of Micromechanics and Microengineering, vol. 20, no. 2, pp. 025016-1-025016-6, Jan. 2010.
56.M. Bakir, G. Huang, D. Sekar, and C. King, "3D system integration: power delivery, cooling, and signaling," IETE Technical Review, vol. 26, no. 6, pp. 407-416, 2009. (invited)
57.D. Sekar, C. King, B. Dang, M. Bakir, J. Meindl, "Removing heat from 3D stacked chips," Future Fab International, Vol. 29, no. 4, pp. 80-85, Apr. 2009. (invited)
58.M. Bakir, A. Glebov, M. Lee, P. Kohl, and J. Meindl, "Mechanically flexible chip-to-substrate optical interconnections using optical pillars," IEEE Trans. Adv. Packaging, vol. 31, no. 1, pp. 143-153, Feb. 2008.
59.M. Bakir, B. Dang, O. Ogunsola, R. Sarvari, and J. Meindl, "Electrical and optical chip I/O interconnections for gigascale systems," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2426-2437, Sep. 2007.
60.O. Ogunsola, H. D. Thacker, B. L. Bachim, M. S. Bakir, J. Pikarsky, T. K. Gaylord, and J. D. Meindl, "Chip-level waveguide-mirror-pillar optical interconnect structure," IEEE Photon. Technol. Lett., vol. 18, no. 15, pp. 1672-1674, Aug. 2006.
61.L. Glebov, D. Bhusari, P. Kohl, M. Bakir, J. Meindl, and M. G. Lee, "Flexible pillars for displacement compensation in optical chip assembly," IEEE. Photon. Technol. Lett., vol. 18, no. 6, pp. 974-976, Apr. 2006.
62.B. Dang, M. S. Bakir, and J. D. Meindl, "Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink," IEEE Electron Device Letters, vol. 27, no. 2, pp. 117-119, Feb. 2006.
63.M. S. Bakir, B. Dang, R. Emery, G. Vandentop, P. A. Kohl, and J. D. Meindl, "Sea of Leads compliant I/O interconnection process integration for the ultimate enabling of chips with low-k interlayer dielectrics," IEEE J. Adv. Packag., vol. 28, no. 3, pp. 488-494, Aug. 2005.
64.B. Dang, M. S. Bakir, C. S. Patel, H. D. Thacker, and J. D. Meindl, "Sea-of-Leads MEMS I/O interconnects for low-k IC packaging," IEEE J. Microelectromechanical Systems, vol. 15, no. 3, pp. 523-530, June 2005.
65.M. S. Bakir, C. O. Chui, A. K. Okyay, K. C. Saraswat, and J. D. Meindl, "Integration of optical polymer pillars chip I/O interconnections with Si MSM photodetectors," IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1084-1090, July 2004.
66.M. S. Bakir and J. D. Meindl, "Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration," IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1069-1077, July 2004.
67.M. S. Bakir, T. K. Gaylord, O. O. Ogunsola, E. G. Glytsis, and J. D. Meindl, "Optical transmission of polymer pillars for chip I/O optical interconnections," IEEE Photon. Technol. Lett., vol. 16, no. 1, pp. 117-119, Jan. 2004.
68.M. S. Bakir, T. K. Gaylord, K. P. Martin, and J. D. Meindl, "Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections," IEEE Photon. Technol. Lett., vol. 15, no. 11, pp. 1567-1569, Nov. 2003.
69.M. S. Bakir, H. A. Reed, H. D. Thacker, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)," IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2039-2048, Oct. 2003.
70.D. C. Keezer, C. S. Patel, M. S. Bakir, Q. Zhou, and J. D. Meindl, "Electrical test strategies for a wafer-level packaging technology," IEEE Trans. Electron. Packag. Manufac., vol. 26, no. 4, pp. 267-272, Oct. 2003.
71.M. S. Bakir, H. A. Reed, A. V. Mule, J. Jayachandran, P. A. Kohl, T. K. Gaylord, K. P. Martin, and J. D. Meindl, "Chip-to-module interconnections using 'Sea of Leads' technology," MRS Bulletin, vol. 28, no. 1, pp. 61-67, Jan. 2003. (invited)
Refereed Conference Publications
1.P. K. Jo, M. Zia, J. L. Gonzalez, and M. S. Bakir, "Dense and highly elastic compressible microinterconnects (CMIs) for electronic microsystems," in Proc. 66th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May. 2017.
2.H. Oh, X. Zhang, P. K. Jo, G. S. May, and M. S. Bakir, "Monolithic-like heterogeneously integrated microsystems using dense low-loss interconnects," in Proc. IEEE Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Phoenix, AZ, Jan. 2017. (invited).
3.W. Wahby, T. E. Sarvey, H. Sharma, H. Esmaeilzadeh, and M. S. Bakir, "The impact of 3D stacking on GPU-accelerated deep neural networks an experimental study," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Nov. 2016.
4.Y. Zhang, X. Zhang, W. Wahby, and M. S. Bakir, "Design considerations for 2.5-D and 3-D integration accounting for thermal constraints," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Nov. 2016.
5.C. Wan, T. K. Gaylord, and M. S. Bakir, "Grating design for 3-D interconnections of waveguides in overlaid chips using the RCWA-EIS method," in Frontiers in Optics, Rochester, NY, Oct. 2016.
6.W. Wahby and M. S. Bakir, "Impact of Alternate Metals on Routing in Scaled Monolithic 3DICs," in Proc. SRC Techcon, Austin, TX, Sep. 2016.
7.Y. Zhang, T. E. Sarvey, Y. Zhang, M. Zia and M. S. Bakir, "Numerical and experimental exploration of thermal isolation in 3D systems using air gap and mechanically flexible interconnects," in IEEE International Interconnect Technology Conf. / Advanced Metallization Conf. (IITC/AMC), San Jose, CA, May. 2016.
8.P. Asrar, X. Zhang, C. E. Green, P. A. Kottke, T. E. Sarvey, A. G. Fedorov, M. S. Bakir, Y. K. Joshi, "Flow visualization of two phase flow of R245fa in a microgap with integrated staggered pin fins," in Thermal Measurement, Modeling & Management Symposium (SEMI-THERM), San Jose, CA, Mar. 2016.
9.R. Abbaspour, D. C. Woodrum, P. A. Kottke, T. E. Sarvey, C. E. Green, Y. K. Joshi, A. G. Fedorov, S. K. Sitaraman, and M. S. Bakir, "Combined finned microgap with dedicated extreme-microgap hotspot flow for high performance thermal management," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.
10.M. H. Nasr, C. E. Green, P. E. Kottke, X. Zhang, T. E. Sarvey, Y. K. Joshi, M. S. Bakir, A. G. Fedorov, "Extreme-microgap based hotspot thermal management with refrigerant flow boiling," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.
11.P. Asrar, X. Zhang, C. E. Green, P. A. Kottke, T. E. Sarvey, A. G. Fedorov, M. S. Bakir, and Y. K. Joshi, "Flow boiling of R245fa in a microgap with integrated staggered pin fins," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.
12.Y. Song, R. Abbaspour, M. S. Bakir, and S. K. Sitaraman, "Thermal annealing effects on copper microstructure in Through-Silicon-Vias," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.
13.D. C. Woodrum, X. Zhang, P. A. Kottke, Y. K. Joshi, A. G. Fedorov, M. S. Bakir, and S. K. Sitaraman, "Reliability assessment of hydrofoil-shaped micro-pin fins subjected to high performance coolant," in IEEE The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.
14.X. Zhang, M. H. Nasr, D. C. Woodrum, C. E. Green, P. A. Kottke, T. E. Sarvey, Y. K. Joshi, S. K. Sitaraman, A. G. Fedorov, and M. S. Bakir, "Design, microfabrication and thermal characterization of the hotspot cooler testbed for convective boiling experiments in extreme-micro-gap with integrated micropin-fins and heat Loss minimization," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.
15.H. Oh, X. Zhang, G. May, and M. Bakir, "High-frequency analysis of embedded microfluidic cooling within 3-D ICs using a TSV testbed," in Proc. 66th IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May. 2016.
16.X. Zhang, V. Kumar, R. Alapati, A. Naeemi and M. S. Bakir, "Interconnect performance in 3D ICs accounting TSV frequency-dependent capacitance and resistive on-chip wires: model, fabrication, and testing," in Proc. SRC Techcon, Austin, TX, Sep. 2015.
17.M. Zia, T. Chi, C. Zhang, P. Thadesar, T. Hookway, J. Gonzalez, T. McDevitt, H. Wang, and M. S. Bakir, "A microfabricated electronic microplate platform for low-cost repeatable bio-sensing applications," in Proc. IEEE International Electron Devices Meeting (IEDM), Washington, DC, Dec. 2015.
18.T. E. Sarvey, Y. Zhang, L. Zheng, P. Thadesar, R. Gutala, C. Cheung, A. Rahman, M. S. Bakir, "Embedded cooling technologies for densely integrated electronic systems," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Oct. 2015. (invited)
19.M. Zia, C. Zhang, P. Thadesar, T. Hookway, T. Chi, J. Gonzalez, T. McDevitt, H. Wang, and M. S. Bakir, "Fabrication of and cell growth on silicon membranes with high density TSVs for bio-sensing applications," in Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), Atlanta, GA, Oct. 2015.
20.H. Oh, G. May, and M. Bakir, "Silicon interposer platform with low-loss through-silicon vias using air," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Sendai, Japan, Aug. 2015.
21.X. Zhang, X. Han, T. E. Sarvey, C. E. Green, P. A. Kottke, A. G. Fedorov, Y. Joshi, and M. S. Bakir, "3D IC with embedded microfluidic cooling: technology, thermal performance, and electrical implications," in Proc. Int. Tech. Conf. and Expo. Packaging and Integration of Electronic and Photonic Microsystems and Int. Conf. Nanochannels, Microchannels, and Minichannels (InterPACKICNMM), San Francisco, CA, July 2015.
22.C. E. Green, P. E. Kottke, T. E. Sarvey, A. G. Federov, Y. Joshi, M. S. Bakir, "Performance and integration implications of addressing localized hotspots through two approaches: clustering of micro pin-fins and dedicated microgap coolers," in Proc. Int. Tech. Conf. and Expo. Packaging and Integration of Electronic and Photonic Microsystems and Int. Conf. Nanochannels, Microchannels, and Minichannels (InterPACKICNMM), San Francisco, CA, July 2015.
23.D. C. Woodrum, T. Sarvey, M. S. Bakir and S. K. Sitaraman, "Reliability study of micro-pin fin array for on-chip cooling," in Proc. 65th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 2015.
24.P. Thadesar and M. Bakir, "Fabrication and characterization of mixed-signal polymer-enhanced silicon interposer featuring photodefined coax TSVs and high-Q inductors," in Proc. 65th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 2015.
25.L. Zheng, Y. Zhang, and M. Bakir, "Silicon interposer with embedded microfluidic cooling for high-performance computing systems," in Proc. 65th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 2015.
26.C. Zhang, H. S. Yang, T. E. Sarvey, and M. S. Bakir, "Au-NiW mechanically flexible interconnects (MFIs) for rematable 3D integration," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Cork, Ireland, Dec. 2014.
27.Y. Zhang, T. E. Sarvey, and M. S. Bakir, "Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Cork, Ireland, Dec. 2014.
28.W. Wahby, L. Zheng, Y. Zhang, and M. Bakir, "A virtual integration platform for 3DIC design space exploration," in Proc. SRC Techcon, Austin, TX, Sep. 2014.
29.P. Thadesar, L. Zheng, and M. Bakir, "Low-loss silicon interposer for three-dimensional system integration with embedded microfluidic cooling," in Proc. IEEE VLSI Technology Symposium, Honolulu, HI, June 2014.
30.C. Zhang, H.S. Yang, M. Bakir, "Mechanically flexible interconnects with highly scalable pitch and large stand-off height for silicon interposer tile and bridge interconnection," in Proc. 64th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2014.
31.T. E. Sarvey, Y. Zhang, Y. Zhang, H. Oh, and M. S. Bakir, "Thermal and electrical effects of staggered micropin-fin dimensions for cooling of 3D microsystems,"in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Orlando, FL, May 2014.
32.H. S. Yang, C. Zhang, M. Zia, L. Zheng, M. Bakir, "Interposer-to-interposer electrical and silicon photonic interconnection platform using silicon bridge," in Proc. IEEE Photonics Society Optical Interconnects Conf., Coronado, CA, May 2014.
33.H. Oh, Y. Zhang, L. Zheng, and M. Bakir,"Electrical interconnect and microfluidic cooling within 3D ICs and silicon interposer," in Proc. Int. Tech. Conf. and Expo. Packaging and Integration of Electronic and Photonic Microsystems and Int. Conf. Nanochannels, Microchannels, and Minichannels (InterPACKICNMM), Chicago, IL, Aug. 2014.
34.S. A. Isaacs, Y. Joshi, Y. Zhang, M. Bakir, and Y. J. Kim, "Two-phase flow and heat transfer in pin-fin enhanced micro-gaps with non-uniform heating," in Proc. ASME Int. Conf. on Micro/Nanoscale Heat and Mass Transfer, Hong Kong, China, Dec. 2013.
35.W. Wahby, A. Dembla, and M. Bakir, "Evaluation of 3DICs and fabrication of monolithic interlayer vias," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Oct. 2013.
36.Y. Zhang, H. Oh, and M. Bakir, "Within-tier cooling and thermal isolation technologies for heterogeneous 3D ICs," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Oct. 2013.
37.Best in Session Paper Award: P. Thadesar and M. Bakir "Fabrication and wideband characterization of novel photodefined polymer-embedded vias for silicon interposers," in Proc. SRC TECHCON, Austin, TX, Sep. 2013.
38.V. Kumar, L. Zheng, M. Bakir, and A. Naeemi, "Compact modeling and optimization of fine-pitch interconnects for silicon interposers", in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.
39.H. Oh, A. Dembla, Y. Zhang, and M. Bakir "High aspect ratio TSVs in micro-pinfin heat sinks for 3D ICs," in Proc. SRC TECHCON, Austin, TX, Sep. 2013.
40.Y. Zhang, L. Zheng, and M. Bakir, "Tier-independent microfluidic cooling for heterogeneous 3D ICs with nonuniform power dissipation," in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.
41.J. Myung Gu, P. Thadesar, A. Dembla, S. Jeen Hong, M. Bakir, and G. May, "Endpoint detection using optical emission spectroscopy in TSV fabrication," in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.
42.P. Thadesar, A. Dembla, Devin Brown, and M. S. Bakir, "Novel through-silicon via technologies for 3D system integration," in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.
43.P. Thadesar and M. Bakir, "Fabrication and characterization of novel photodefined polymer-enhanced through-silicon vias for silicon interposers," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.
44.H.S. Yang, C. Zhang, M.S. Bakir, "A low-cost self-alignment structures for heterogeneous 3D integration," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.
45.L. Zheng and M. Bakir, "Design, fabrication and assembly of novel electrical and microfluidic I/Os for 3-D chip stack and silicon interposer," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.
46.P. Thadesar, J. M. Gu, A. Dembla, S. J. Hong, G. S. May and M. S. Bakir, "Novel photodefined polymer-clad through-silicon via technology integrated with end point detection using optical emission spectroscopy," in Proc. 24th Annual SEMI Advanced Semiconductor Manufacturing Conf. (ASMC), Saratoga Springs, NY, May 2013.
47.P. Thadesar and M. Bakir, "Novel low-loss photodefined electrical TSVs for silicon interposers," Topical Workshop on Advanced 3D Packaging, 9th IMAPS Int. Conf. and Exhibition on Device Packaging, Scottsdale/Fountain Hills, AZ, Mar. 2013.
48.S. A. Isaacs, Y. J. Kim, A. J. McNamara, Y. Joshi, Y. Zhang, and M. Bakir, "Two-phase flow and heat transfer in pin-fin enhanced micro-gaps," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), San Diego, CA, May. 2012.
49.P. Thadesar and M. Bakir, "Silicon interposer featuring novel electrical and optical TSVs," in Proc. ASME International Mechanical Engineering Congress and Exposition, Houston, TX, Nov. 2012.
50.L. Zheng and M. Bakir, "Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer," in Proc. IEEE International System-on-Chip Conf. (SoCC), 2012.
51.A. Dembla, Y. Zhang, and M. Bakir, "Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs," in Proc. SRC TECHCON, Austin, TX, Sep. 2012.
52.A. Dembla, Y. Zhang, and M. Bakir, "High aspect ratio TSVs in micropin-fin heat sinks for 3D ICs," in Proc. IEEE Int. Conf. Nanotechnology, Birmingham, England, Aug. 2012.
53.A. Dembla, Y. Zhang, and M. Bakir, "Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs," in Proc. IEEE International Interconnect Technology Conf. (IITC), San Jose, CA, June 2012.
54.Outstanding Interactive Presentation Paper Award: Y. Zhang, A. Dembla, Y. Joshi, and M. Bakir, "3D stacked on-demand microfluidic cooling for high performance 3D ICs" in Proc. 62nd IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, 2012.
55.C. Zhang, H. S. Yang, and M. Bakir, "Gold passivated mechanically flexible interconnects (MFIs) with high elastic deformation," in Proc. 62nd IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, 2012.
56.Student Paper Award: H. S. Yang and M. Bakir, "Design and wafer-level fabrication of positive self-alignment structures for improved vertical optical coupling," in IMAPS/IEEE-CPMT Advanced Technology Workshop on Optoelectronic Packaging, Irvine, CA, June 2011.
57.A. Dembla, D. Brown, and M. Bakir, "Nanofabrication of high aspect ratio nanoscale TSVs," in Proc. Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), Las Vegas, NV, May. 2011.
58.A. Dembla, D. Brown, and M. Bakir, "Nanofabrication of ultra high density nanoscale TSVs," in SRC Techcon, Austin, TX, Sep. 2011.
59.Best in Session Paper Award: P. Modarres, R. Ravindran, M. Bakir, "Three-dimensional integrated CMOS and high density biosensor array using through-silicon vias," in SRC Techcon, Austin, TX, Sep. 2011.
60.L. Zheng, G. Huang, and M. Bakir, "Power delivery and thermal management for high-performance 3D chip stack," in SRC Techcon, Austin, TX, Sep. 2011.
61.M. Parekh, P. Thadesar and M. Bakir, "Electrical, optical, and fluidic through-silicon vias for silicon interposer applications," in Proc. 61st IEEE Electronic Components and Technology Conf., Lake Buena Vista, FL, May 2011.
62.Y. Zhang, C. King, J. Zaveri, Y. J. Kim, V. Sahu, Y. Joshi, and M. Bakir, "Coupled electrical and thermal 3D IC centric microfluidic cooling heat sink design and technology," in Proc. 61st IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2011.
63.M. Bakir, P. Thadesar, C. King, J. Zaveri, H. Yang, C. Zhang, Y. Zhang, "Revolutionary innovation in system interconnection: A new era for the IC," in Proc. Photonics West, Proc. of SPIE, Feb. 2011.
64.Y. Zhang, J. Zaveri, C. King, and M. Bakir, "Coupled electrical and thermal 3D IC centric microfluid heat sink design," in Proc. SRC Techcon, 2010.
65.Best in Session Paper Award: H. S. Yang and M. Bakir, "3D integration of CMOS and MEMS using MFI and TSV," in SRC Techcon, 2010.
66.H. S. Yang, R. Ravindran, M. S. Bakir, J.D. Meindl, "A 3D interconnect system for large biosensor array and CMOS signal-processing IC integration," IEEE Interconnect Technology Conf. (IITC), 2010 International, 6-9 June 2010
67.R. Ravindran, J. A. Sadie, K. E. Scarberry, H. S. Yang, M. S. Bakir, J. F. McDonald, and J. D. Meindl, "Biochemical sensing with an arrayed silicon nanowire platform," in Proc. IEEE Electronic Components and Technol. Conf., pp. 1015-1020, 2010.
68.H. S. Yang and M. Bakir, "Mechanically flexible interconnects with high out-of-plane range-of- movement and thick wafer through silicon vias for CMOS and MEMS Integration," in Proc. IEEE Electronic Components and Technol. Conf., pp. 822-828, 2010.
69.C. King, J. Zaveri, M. Bakir, and J. Meindl, "Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs," in Proc. IEEE Electronic Components and Technology Conf., pp. 822-828, 2010.
70.H. S. Yang and M. Bakir, "Interconnect technologies for 3D integration of CMOS and MEMS," in Proc. MRS Spring Meeting, 2010. (invited)
71.Best Student Paper Award and Best Paper in Session Award: J. Zaveri, C. King Jr., H.S. Yang, M.S. Bakir, "Wafer level batch fabrication of silicon microchannel heat sinks and electrical through silicon vias for 3D ICs," IMAPS 42nd International Symposium on Microelectronics, 2009.
72.J. Zaveri, C. King, H. Yang, and M. Bakir, "Wafer level batch fabrication of Silicon microchannel heat sinks and electrical through silicon vias" in Proc. SRC TECHCON, 2009.
73.Best in Session Paper Award: C. King, J. Zaveri, H. S. Yang, M. Bakir, and J. Meindl "Electro-fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs," in Proc. SRC TECHCON, 2009.
74.M. Bakir and G. Huang, "Power delivery, signaling and cooling in 3D integrated systems," in Proc. MRS Spring Meeting, 2009. (invited)
75.M. S. Bakir, C. King, D. Sekar, and B. Dang, "Electrical, optical, and fluidic interconnect networks for 3D heterogeneous integrated systems," in Proc. IEEE Avionics, Fiber-Optics and Photonics Conf., 2008, pp.7-8. (invited)
76.M. S. Bakir, C. King, D. Sekar, H. Thacker, B. Dang, G. Huang, A. Naeemi, and J. D. Meindl, "3D heterogeneous integrated systems: liquid cooling, power delivery, and implementation," in Proc. IEEE Custom Integrated Circuits Conf., 2008, pp.663-670. (invited)
77.C. King, D. Sekar, M. Bakir, B. Dang, J. Pikarsky, and J. Meindl, "3D stacking of chips with electrical and microfluidic I/O interconnects," in Proc. SRC TECHCON, 2008.
78.Best Student Conf. Paper Award: D. Sekar, C. King, B. Dang, T. Spencer, H. Thacker, P. Joseph, M. Bakir, and J. Meindl, "A 3D-IC technology with integrated microchannel cooling," in Proc. IEEE Int. Interconnect Technol. Conf., 2008, pp. 13-15. (Figures from paper were used to publicize Conf.) Paper featured in multiple trade journal articles.
79.Motorola Electronic Packaging Fellowship Student Paper Award ($21,000 stipend): C. King, D. Sekar, M. Bakir, B. Dang, J. Pikarsky, and J. Meindl, "3D stacking of chips with electrical and microfluidic I/O interconnects," in Proc. Electronic Components and Technol. Conf., 2008, pp. 1-7.
80.C. King, D. Sekar, M. Bakir, B. Dang, J. Pikarsky, J. Meindl, "Assembly techniques for microfluidic networks in three-dimensional integrated circuits," SRC TECHCON, 2007.
81.G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. Meindl, "Power delivery for 3D chip stacks: physical modeling and design implication," in Proc. IEEE 16th Conf. Electrical Performance and Electronic Packaging, 2007, pp. 205-208.
82.M. Bakir, B. Dang, G. Huang, and J. Meindl, "Limits and opportunities for heat removal and power delivery to gigascale systems," in Proc. SEMATECH Thermal and Design Issues in 3D ICs, 2007. (invited) Paper featured in multiple trade journal articles.
83.Best Invited Conf. Paper Award: M. Bakir, B. Dang, and J. Meindl, "Revolutionary nanosilicon ancillary technologies for ultimate-performance gigascale systems," in Proc. IEEE Custom Integrated Circuits Conf., 2007, pp. 421-428. (invited) (Figures from paper were posted on the Conf. website)
84.M. Bakir, B. Dang, and J. Meindl, "Electrical, optical, and thermofluidic chip I/O interconnections," in Proc. ASME InterPACK, 2007.
85.Outstanding Conf. Paper Award: M. Bakir, B. Dang, O. Ogunsola, and J. Meindl, "Trimodal' wafer-level package: fully compatible electrical, optical, and fluidic chip I/O interconnects," in Proc. Electronic Components and Technol. Conf., 2007, pp. 585-592.
86.M. Bakir and J. Meindl, "Fully compatible low cost electrical, optical, and fluidic I/O interconnect networks for ultimate performance 3D gigascale systems," in Proc. Int. 3D System-in-Chip Conf., 2007. (invited, Tokyo, Japan)
87.M. S. Bakir, P. A. Kohl, A. L. Glebov, E. Elce, D. Bhusari, M. G. Lee, and J. D. Meindl, "Flexible polymer pillars for optical chip assembly: materials, structures, and characterization," in Proc. SPIE Photonics West, 2007, pp. 792803-1 - 792803-8. (invited)
88.H. Thacker, O. Ogunsola, A. Carson, M. Bakir, and J. Meindl, "Optical through-wafer interconnects for 3D hyper-integration," in Proc. IEEE LEOS, 2006, pp. 28-29.
89.K.-N. Chen, M. Bakir, J. Meindl, and R. Reif, "Copper interconnect bonding for polymer pillar I/O interconnects and three-dimensional (3D) integration applications," in Proc. TMS Electronics Materials Conf., 2006.
90.Best Student Conf. Paper Award: O. Ogunsola, H. Thacker, B. Bachim, M. Bakir, T. Gaylord, J. Meindl, "Polymer pillars as optical I/O for gigascale chips using mirror-terminated waveguides," IEEE Int. Interconnect Technol. Conf.,2006, pp. 170- 172.(Figures from paper were used to publicize Conf.) Paper featured in multiple trade journal articles.
91.H. Ate, M. Bakir, S. Allen, P. Kohl, "Fabrication of compliant, copper-based chip-to-substrate connections," in Proc. Electronic Components and Techn. Conf., 2006, pp. 29- 34.
92.M. Bakir, B. Dang, H. Thacker, O. Ogunsola, R. Ogra, and J. Meindl, "Dual-mode electrical-optical flip-chip I/O interconnects and a compatible probe substrate for wafer-level testing," in Proc. Electronic Components and Technol. Conf., 2006, pp. 768-775.
93.Best Student Conf. Paper Award: B. Dang, P. Joseph, M. Bakir, T. Spencer, P.A. Kohl, J.D. Meindl, "Wafer level microfluidic cooling interconnects for GSI," in Proc. IEEE Int. Interconnect Technol. Conf., 2005, pp.180-182.(Figures from paper were used to publicize Conf.) Paper featured in multiple trade journal articles.
94.B. Dang, P. Joseph, M. Bakir, P. Kohl, J. Meindl, "Fabrication, assembly and testing of an on-chip microfluidic heat sink," in Proc. Int. Symp. of Microelectronics, 2005, TP2:pp.1-5.
95.B. Dang, P. J. Joseph, X. Wei, M. S. Bakir, P. A. Kohl, Y. K. Joshi, and J. D. Meindl, "A chip-scale cooling scheme with on-chip heat sink and integrated microfluidic I/O interconnects," in Proc. ASME InterPACK, 2005, paper num. 73416.
96.H. Thacker, O. Ogunsola, M. Bakir, J. Meindl, "Probe Module for Wafer-level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects," in Proc. ASME InterPACK, 2005.
97.H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, "High-density probe substrate for testing optical interconnects," in Proc. IEEE Int. Interconnect Technol. Conf., 2005, pp.159-161.
98.H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, "Probe module for wafer-level testing of gigascale chips with polymer pillar-based electrical and optical I/O interconnects," in Proc. SRC TECHCON, 2005.
99.O. Ogunsola, H. Thacker, B. Bachim, M. Bakir, T. Gaylord, J. Meindl, "Mirror-enabled polymer pillar optical I/O interconnects for gigascale integration," in Proc. SRC TECHCON, 2005.
100.B. Dang, P. J. Joseph, M. S. Bakir, P. A. Kohl, Y. K. Joshi, and J. D. Meindl, "A chip-scale cooling scheme with on-chip heat sink and integrated microfluidic I/O interconnects," in Proc. SRC TECHCON, 2005.
101.M. S. Bakir and J. D. Meindl, "Wafer-level packaging of optoelectronic devices using Sea of Leads electrical and optical I/O interconnections," in Proc. IEEE LEOS Annual Meeting, 2004, pp. 583-584. (invited)
102.B. Dang, M. S. Bakir, K. P. Martin, and J. D. Meindl, "Assembly and reliability assessment of Sea-of-Leads compliant wafer level package," in Proc. IMAPS Int. Symp. on Microelectronics, 2004, pp. 7-14.
103.K. Shakeri, M. S. Bakir, and J. D. Meindl, "Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution," in Proc. IEEE Int. System-on-Chip Conf., 2004, pp. 78-81.
104.B. Dang, C. Patel, H. D. Thacker, M. S. Bakir, K. P. Martin, and J. D. Meindl, "Optimal implementation of Sea-of-Leads (SoL) compliant interconnect technology," in Proc. IEEE Int. Interconnect Technol. Conf., 2004, pp. 99-101.
105.M. S. Bakir and J. D. Meindl, "Integrated electrical, optical, and thermal high density and compliant wafer-level chip I/O interconnections for gigascale integration," in Proc. Electronic Components and Technol. Conf., 2004, pp. 1-6.
106.M. S. Bakir, B. Dang, R. Emery, G. Vandentop, K. P. Martin, P. A. Kohl, and J. D. Meindl, "Chip integration of Sea of Leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics," in Proc. Electronic Components and Technol. Conf., 2004, pp. 1167-1173.
107.M. S. Bakir, R. A. Villalaz, O. O. Ogunsola, T. K. Gaylord, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of polymer pillars: dual-mode electrical-optical input/output interconnections," in Proc. Int. Interconnect Technol. Conf., 2003, pp. 77-79.
108.M. S. Bakir, A. Mule, T. Gaylord, P. Kohl, K. Martin, and J. Meindl, "Sea of dual-mode polymer pillar I/O interconnections for gigascale integration," in Proc. Int. Solid-State Circuits Conf., 2003, pp. 372-373. (Figures from paper were used to publicize Conf.) Paper featured in multiple trade journal articles.
109.A. V. Mule, M. S. Bakir, J. Jayachandran, R. Villalaz, H. Reed, N. Agrawal, S. Ponoth, J. Plawsky, P. Persans, P. Kohl, K. Martin, E. Glytsis, T. Gaylord, and J. Meindl, "Optical waveguides with embedded air-gap cladding integrated within a Sea-of-Leads (SoL) wafer-level package," in Proc. Int. Interconnect Technol. Conf., 2002, pp. 122-124. Paper featured in multiple trade journal articles.
110.M. S. Bakir, H. D. Thacker, Z. Zhou, K. P. Martin, and J. D. Meindl, "Sea of leads microwave characterization and process integration with FEOL & BEOL," in Proc. Int. Interconnect Technol. Conf., 2002, pp. 116-118.
111.H. D. Thacker, M. S. Bakir, D. Keezer, K. P. Martin, and J. D. Meindl, "Compliant probe substrates for testing high pin-count chip scale packages," in Proc. Electronic Components and Technol. Conf., 2002, pp. 1188-1193.
112.Best Conf. Paper Award: M. S. Bakir, H. A. Reed, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of Leads ultra-high density compliant wafer level packaging technology," in Proc. Electronic Components and Technol. Conf., 2002, pp. 1087-1094. ; Paper featured in multiple trade journal articles.
113.M. S. Bakir, H. A. Reed, A. V. Mule, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of Leads characterization and design for compatibility with board level optical waveguide interconnection," in Proc. Custom Integrated Circuits Conf., 2002, pp. 491-494.
114.J. D. Meindl, R. Venkatesan, J. A. Davis, J. Joyner, A. Naeemi, P. Zarkesh-Ha, M. S. Bakir, T. Mule, P. A. Kohl, and K. P. Martin, "Interconnecting device opportunities for gigascale integration (GSI)," in Proc. Int. Electron Devices Meeting, 2001, pp. 525-528.
115.H. A. Reed, M. S. Bakir, C. S. Patel, K. P. Martin, J. D. Meindl, and P. A. Kohl, "Compliant wafer level package with embedded air-gaps for Sea of Leads I/O interconnections," in Proc. Int. Interconnect Technol. Conf., 2001, pp. 151-153. (invited)
116.A. Naeemi, C. S. Patel, M. S. Bakir, P. Ha-Zarkesh, K. P. Martin, and J. D. Meindl, "Sea of Leads: a disruptive paradigm for a system on a chip," in Proc. Int. Solid State Circuits Conf., 2001, pp. 280-281.
Conference Tutorials
1. Heat Removal and Power Delivery for 3D Integration, IEEE Int. Solid State Circuits Conf (ISSCC) 2007. (invited)
2. Chip-level and Input/Output Interconnects for Gigascale SoCs: Limits and Opportunities, IEEE System-on-Chip Conf. 2006, with A. Naeemi.
Patents
1. M. Bakir, D. Sekar, B. Dang, C. King, and J. Meindl, "3-D ICs with microfluidic interconnects and methods of constructing same," US patent no. 7,928,563, assigned to Georgia Tech Research Corporation, , issued April 19, 2011.
2. P. Kohl, A. He, T. Spencer, M. Bakir, "High performance integrated circuit interconnect devices and structures," US patent no. 7,798,817, assigned to Georgia Tech Research Corporation, issued September 21, 2010.
3. A. Mule, H. Thacker, M. Bakir, J. Meindl, T. Gaylord, K. Martin, and P. Kohl, "High input/output density optoelectronic probe card for wafer-level test of electrical and optical interconnect components, methods of fabrication, and methods of use," U.S. patent no. 7,554,347, assigned to Georgia Tech Research Corporation, issued Jun. 30th, 2009.
4. M. Bakir and J. Meindl, "Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof," U.S. patent no. 7,468,558 , issued Dec. 23rd, 2008.
5. M. S. Bakir and J. D. Meindl, "Microfluidic, optical, and electrical input output interconnects, methods of fabrication thereof, and methods of use thereof," US patent # 7,266,267, Sept. 4, 2007.
6. M. Bakir and J. Meindl, "Devices having compliant wafer-level input/output interconnections and packages using pillars and methods of fabrication thereof," U.S. patent number 7,135,777 assigned to Georgia Tech Research Corporation, issued Nov. 14, 2006.
7. M. Bakir, J. Meindl, and C. Patel, "Devices having compliant wafer-level packages with pillars and methods of fabrication," U.S. patent number 7,132,736 assigned to Georgia Tech Research Corporation, issued Nov. 7, 2006.
8. M. Bakir and J. Meindl, "Dual-mode/function optical and electrical interconnects, methods of fabrication thereof, and methods of use thereof," U.S. patent number 7,099,525 assigned to Georgia Tech Research Corporation, issued Aug. 29, 2006.
9. A. Mule, C. Patel, J. Meindl, T. Gaylord, E. Glytsis, K. Martin, S. Schultz, M. Bakir, H. Reed, P. Kohl, "Guided-wave optical interconnections embedded within a microelectronic wafer-level batch package," U.S. patent number 6,954,576 assigned to Georgia Tech Research Corporation, issued Oct. 11, 2005.
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