@INPROCEEDINGS{8534260, author={P. K. {Jo} and T. {Zheng} and M. S. {Bakir}}, booktitle={2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)}, title={Multi-Die Polylithic Integration Enabled by Heterogeneous Interconnect Stitching Technology (HIST)}, year={2018}, volume={}, number={}, pages={11-13}, keywords={chip scale packaging;fine-pitch technology;integrated circuit interconnections;three-dimensional integrated circuits;wafer level packaging;multidie polylithic integration approach;high-density electronic systems;low-loss electronic systems;signal pathways;assembled anchor chips;multiheight compressible microinterconnects;CMIs;mechanically robust interfaces;electrical measurements;EM simulations;quartz stitch-chips;low-loss signal interconnection;robust interconnection;3D face-to-face electrical interconnections;surface-embedded chips;HIST approach;low-energy electronic systems;polylithic integration approach;Heterogeneous Interconnect Stitching Technology;size 90.0 mum;size 500.0 mum;Substrates;Silicon;Integrated circuit interconnections;Fabrication;Electrical resistance measurement;Gold;Semiconductor device measurement;Heterogeneous integration;Polylithic integration;Compliant interconnects}, doi={10.1109/EPEPS.2018.8534260}, ISSN={2165-4107}, month={Oct},}