@INPROCEEDINGS{8811337,
author={P. K. {Jo} and T. {Zheng} and M. S. {Bakir}},
booktitle={2019 IEEE 69th Electronic Components and Technology Conference (ECTC)},
title={Polylithic Integration of 2.5D and 3D Chiplets Using Interconnect Stitching},
year={2019},
volume={},
number={},
pages={1803-1808},
keywords={integrated circuit design;integrated circuit interconnections;three-dimensional integrated circuits;multiheight Compressible MicroInterconnects;CMIs;mechanically robust interfaces;surface-embedded chips;robust interconnection;stitch-chip channels;fused silica stitch-chip;polylithic integration;3D chiplets;interconnect stitching;heterogeneous dice;high-density electronic systems;dense signal pathways;3D face-to-face electrical interconnection;anchor chips;size 500.0 mum;size 90.0 mum;loss 0.6 dB;Electronic components;Conferences;Three-dimensional displays;Very large scale integration;Hafnium;Manufacturing;Compliant interconnects;2.5D and 3D ICs;Heterogeneous integration},
doi={10.1109/ECTC.2019.00278},
ISSN={0569-5503},
month={May},}