@ARTICLE{1262379,
author={D. C. {Keezer} and C. S. {Patel} and M. S. {Bakir} and {Qing Zhou} and J. D. {Meindl}},
journal={IEEE Transactions on Electronics Packaging Manufacturing},
title={Electrical test strategies for a wafer-level packaging technology},
year={2003},
volume={26},
number={4},
pages={267-272},
keywords={wafer-scale integration;integrated circuit packaging;integrated circuit manufacture;integrated circuit testing;thermal management (packaging);integrated circuit interconnections;wafer-level packaging;WLP technology;compliant electrical leads;integrated circuits;wafer form;photolithographic steps;electrical testing;interconnect substrate;thermal mismatch;Wafer scale integration;Lead;Circuit testing;Contacts;Integrated circuit technology;Integrated circuit packaging;Fabrication;Costs;Bonding;Assembly},
doi={10.1109/TEPM.2003.822063},
ISSN={1558-0822},
month={Oct},}