@ARTICLE{1492518,
author={M. S. {Bakir} and B. {Dang} and R. {Emery} and G. {Vandentop} and P. A. {Kohl} and J. D. {Meindl}},
journal={IEEE Transactions on Advanced Packaging},
title={Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics},
year={2005},
volume={28},
number={3},
pages={488-494},
keywords={chip-on-board packaging;integrated circuit interconnections;dielectric materials;wafer bonding;microassembling;reflow soldering;encapsulation;lead;compliant leads;I/O interconnect process integration;low-k interlayer dielectrics;sea of leads process integration;wafer level integration;standard semiconductor processes;chip assembly techniques;low-k interlayer dielectric;mechanical stresses;coefficient of thermal expansion;compliant interconnections;encapsulation film;wafer sawing;slippery leads;nickel-oxide nonwettable layer;wafer-level solder reflow;die assembly;thermo-compression bonding;2.7 ohm;Pb;Dielectrics;Assembly;Fabrication;Lead compounds;Microprocessors;Thermal expansion;Thermal stresses;Encapsulation;Sawing;Wafer bonding;Compliant leads;input/output (I/O);interconnects;low-;packaging},
doi={10.1109/TADVP.2005.848386},
ISSN={1557-9980},
month={Aug},}