@ARTICLE{8932458, author={M. O. {Hossen} and B. {Chava} and G. {Van der Plas} and E. {Beyne} and M. S. {Bakir}}, journal={IEEE Transactions on Electron Devices}, title={Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and $\mu$ TSVs}, year={2020}, volume={67}, number={1}, pages={11-17}, abstract={In this article, a power delivery network (PDN) modeling framework for backside-PDN configurations is presented. A backside-PDN configuration contains dense microthrough silicon vias (μTSVs) and power/ground metal stack on the backside of the die. This approach separates the PDN from a conventional signaling network of the back-end-of-the-line (BEOL) and improves power integrity and core utilization. We benchmark this technology with conventional front-side BEOL PDN configurations. Owing to the lower resistivity compared with Cu metal lines for advanced technology nodes, we use ruthenium (Ru)-based buried power rail for PDN modeling. Our analysis shows that the steady-state IR-drop reduces by more than 4× in the backside-PDN configuration, and a simultaneous switching noise analysis shows a significant reduction in transient droops. The framework results are validated with a place-and-route (P&R)-based physical implementation flow. We quantify the area improvement in the actual flow and observe 25%-30% improvement in the backside-PDN configuration. From a PDN modeling framework, the PDN results follow a trend similar to the ones obtained from the block-level P&R of the given configurations. Moreover, we investigate the impacts of package-to-die interconnect pitch, metal-insulator-metalcap density, and input pulse on the PDN performance. In addition, we perform thermal modeling to analyze the thermal implications of the backsidePDN configuration. From a thermal modeling perspective, there is negligible influence from a dielectric bonding layer in the backside-PDN configuration.}, keywords={integrated circuit interconnections;integrated circuit packaging;three-dimensional integrated circuits;power delivery network modeling;backside-PDN configurations;buried power rails;dense microthrough silicon vias;power/ground metal stack;PDN modeling;simultaneous switching noise analysis;transient droops;package-to-die interconnect pitch;metal-insulator-metalcap density;thermal modeling;dielectric bonding layer;Metals;Through-silicon vias;Density measurement;Power system measurements;Integrated circuit interconnections;Rails;Switches;Interconnects;IR-drop;physical design;power delivery;transient droop}, doi={10.1109/TED.2019.2954301}, ISSN={1557-9646}, month={Jan},}