@ARTICLE{9146216, author={P. K. {Jo} and S. K. {Rajan} and J. L. {Gonzalez} and M. S. {Bakir}}, journal={IEEE Transactions on Components, Packaging and Manufacturing Technology}, title={Polylithic Integration of 2.5-D and 3-D Chiplets Enabled by Multi-Height and Fine-Pitch CMIs}, year={2020}, volume={}, number={}, pages={1-1}, abstract={A polylithic integration technology called Heterogeneous Interconnect Stitching Technology (HIST) is explored in this paper. HIST provides both 2.5-D and 3-D integration capabilities enabled by multi-height and fine-pitch Compressible MicroInterconnects (CMIs). ANSYS Workbench simulator is used to optimize and simulate the multi-height and fine-pitch CMIs. A testbed is fabricated and assembled in order to demonstrate the key features of the proposed technology: assembly of an anchor chip with multi-height CMIs (65 μm and 35 μm in height) onto a substrate with a surface-embedded chip (52 μm in thickness) and mechanical bonding using solder bumps. Fine-pitch CMIs (30 μm × 3 μm) is also fabricated and demonstrated in order to meet an ever growing need for higher I/O densities for high-performance computing systems. Electrical resistance characterization results are reported as well as the mechanical characterization of interconnects.}, keywords={2.5-D/3-D package assembly;compliant interconnects;system in package (SiP);heterogeneous integration}, doi={10.1109/TCPMT.2020.3011325}, ISSN={2156-3985}, month={},}