@INPROCEEDINGS{9344081,  author={R. {Saligram} and A. {Kaul} and M. S. {Bakir} and A. {Raychowdhury}},  booktitle={2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)},   title={A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration},   year={2020},  volume={},  number={},  pages={159-164},  abstract={The quest for high yield has motivated significant advancement in 2.5D integrated circuits, where chiplets are integrated on a silicon interposer or a package substrate with high-speed parallel communication among them. These channels for 2.5D integrated systems need to have high data bandwidth per unit length (also called shoreline-BW-density and measured in Gb/s/mm) and lower energy per bit area (measured in pJ/b). Typically, NRZ signalling is used but achieving higher data rates continues to be a major challenge. In this paper we explore PAM4 as an alternative to NRZ for signalling the channels. Simulations show that we can achieve up to 63% more energy-efficiency and 27% higher BW density for 2.5D integrated systems.},  keywords={Semiconductor device measurement;Area measurement;Energy measurement;Length measurement;Energy efficiency;Microstrip;Optical signal processing;Heterogeneous Integration;Coplanar Microstrip;NRZ;PAM4;Channel Operating Margin},  doi={10.1109/VLSI-SOC46417.2020.9344081},  ISSN={2324-8440},  month={Oct},}