@InProceedings{10.1007/978-3-030-81641-4_8,
author="Saligram, Rakshith
and Kaul, Ankit
and Bakir, Muhannad S.
and Raychowdhury, Arijit",
editor="Calimera, Andrea
and Gaillardon, Pierre-Emmanuel
and Korgaonkar, Kunal
and Kvatinsky, Shahar
and Reis, Ricardo",
title="Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication",
booktitle="VLSI-SoC: Design Trends",
year="2021",
publisher="Springer International Publishing",
address="Cham",
pages="149--178",
abstract="Increasing memory bandwidth bottleneck, die cost, lower yields at scaled nodes and need for more compact and power efficient devices have led to sustained innovations in integration methodologies. While the semiconductor market has already started witnessing some of these in product forms, many other techniques are currently under investigation in both academia and industry. In this chapter, we explore a 2.5D integrated system where the interconnects are modelled in the form of coplanar microstrip lines. A model is developed to understand the behavior of these wireline structures and is used to study their signaling characteristics. Generally, the conventional NRZ signaling is used to transmit data. As an alternative, we explore a higher order modulation scheme, namely, PAM4. Through the simulation study, we demonstrate that PAM4 can provide up to 63{\%} better energy efficiency and 27{\%} higher bandwidth density than NRZ.",
isbn="978-3-030-81641-4"
}