lab-member-pic
 

Ankit Kaul

  • Ph.D Alumni

 ankit.kaul@gatech.edu
 
 

Biography

  • PhD candidate in Electrical and Computer Engineering, Georgia Institute of Technology
  • MS in Electrical and Computer Engineering at Georgia Institute of Technology, 2018
  • BE in Electrical and Electronics Engineering at Rashtreeya Vidyalaya College of Engineering (RVCE), Bengaluru, India, 2013

Research Interests

Thesis KAUL-DISSERTATION-2023.pdf

All Publications

  1. M. Manley, A. Victor, H. Park, A. Kaul, M. Kathaperumal and M. S. Bakir, "Heterogeneous Integration Technologies for Artificial Intelligence Applications," in IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 10, pp. 89-97, 2024, doi: 10.1109/JXCDC.2024.3484958.

  2. A. Kaul, M. Manley, J. Read, S. Yu and M. S. Bakir., "Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators," 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2024, pp. 1-2, doi: 10.1109/VLSITechnologyandCir46783.2024.10631345.

  3. M. Manley, A. Kaul and M. S. Bakir, "Design Space Exploration for Power Delivery Network in Next Generation 3D Heterogeneous Integration Architectures," 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), Denver, CO, USA, 2024, pp. 2223-2228, doi: 10.1109/ECTC51529.2024.00378.

  4. J. Sharda, M. Manley, A. Kaul, W. Li, M. Bakir and S. Yu, "Design and Thermal Analysis of 2.5D and 3-D Integrated System of a CMOS Image Sensor and a Sparsity-Aware Accelerator for Autonomous Driving," in IEEE Journal of the Electron Devices Society, vol. 12, pp. 426-432, 2024, doi: 10.1109/JEDS.2024.3354621.

  5. A. Kaul, M. O. Hossen, M. Manley and M. S. Bakir, "Design Considerations for Power Delivery Network and Metal-Insulator-Metal Capacitor Integration in Bridge-Chips for 2.5-D Heterogeneous Integration," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 985-990, doi: 10.1109/ECTC51909.2023.00168. 

  6. W. Li, M. Manley, J. Read, A. Kaul, M. S. Bakir and S. Yu, "H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 10, pp. 1592-1602, Oct. 2023, doi: 10.1109/TVLSI.2023.3299509.

  7. J. Sharda, M. Manley, A. Kaul, W. Li, M. Bakir and S. Yu, "Thermal Modeling of 2.5D Integrated Package of CMOS Image Sensor and FPGA for Autonomous Driving," 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Seoul, Korea, Republic of, 2023, pp. 1-3, doi: 10.1109/EDTM55494.2023.10102948. 

  8. A. Kaul, Y. Luo, X. Peng, M. Manley, Y.-C. Luo, S. Yu and M. S. Bakir, "3-D Heterogeneous Integration of RRAM-Based Compute-In-Memory: Impact of Integration Parameters on Inference Accuracy," in IEEE Transactions on Electron Devices, vol. 70, no. 2, pp. 485-492, Feb. 2023, doi: 10.1109/TED.2022.3231570.

  9. M. Manley, A. Kaul, M. -J. Li and M. S. Bakir, "Ultra-Dense 3D Polylithic Integration Technology", Government Microcircuit Applications & Critical Technology Conf., Miami, FL, Mar. 2022.

  10. T. Zheng, A. Kaul, S. Kochupurackal Rajan, and M. S. Bakir, "Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations," in Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces, B. Keser, and S. Kröhnert, Eds. Wiley, 2021, pp. 261-287.

  11. X. Peng, A. Kaul, M. S. Bakir and S. Yu, "Heterogeneous 3-D Integration of Multitier Compute-in-Memory Accelerators: An Electrical-Thermal Co-Design," in IEEE Transactions on Electron Devices, vol. 68, no. 11, pp. 5598-5605, Nov. 2021.

  12. R. Saligram, A. Kaul, M. S. Bakir, and A. Raychowdhury, “Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication,” in A. Calimera, P.-E. Gaillardon, K. Korgaonkar, S. Kvatinsky, R. Reis (Ed.), VLSI-SoC: Design Trends, (1st ed., pp. 149–178) Springer Cham, 2021.

  13. S. Kochupurackal Rajan, A. Kaul, T Sarvey, G. S. May, and M. S. Bakir, "Design Considerations, Demonstration, and Benchmarking of Silicon Micro-cold Plate and Monolithic Microfluidic Cooling for 2.5D ICs," 71st IEEE Electronic Components and Technology Conf. (ECTC),  Jun. 2021.

  14. S. Kochupurackal Rajan, A. Kaul, T. E. Sarvey, G. S. May and M. S. Bakir, "Monolithic Microfluidic Cooling of a Heterogeneous 2.5-D FPGA With Low-Profile 3-D Printed Manifolds," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 6, pp. 974-982, June 2021.

  15. X. Peng , W. Chakraborty, A. Kaul, W. Shim, M.S. Bakir, S. Datta, S. Yu, "Benchmarking Monolithic 3D Integration for Compute-in-Memory Accelerators: Overcoming ADC Bottlenecks and Maintaining Scalability to 7nm or Beyond," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2020.

  16. A. Kaul, X. Peng, S. Kochupurackal Rajan, S. Yu, and M.S. Bakir, "Thermal Modeling of 3D Polylithic Integration and Implications on BEOL RRAM Performance," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2020. (invited)

  17. R. Saligram, A. Kaul, A. Raychowdhury, and M.S. Bakir, "A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration," in Proc. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), virtual, Salt Lake City, UT, Oct. 2020.

  18. A. Kaul, S. Kochupurackal Rajan, M. O. Hossen, G. S. May, and M. S. Bakir, "BEOL-Embedded 3D Polylithic Integration: Thermal and Interconnection Considerations," 70th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2020.

  19. T. E. Sarvey, A. Kaul, S. K. Rajan, A. Dasu, R. Gutala, and M. S. Bakir, "Microfluidic Cooling of a 14-nm 2.5-D FPGA With 3-D Printed Manifolds for High-Density Computing: Design Considerations, Fabrication, and Electrical Characterization," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 12, pp. 2393-2403, 2019.