1. A. Kaul, Y. Luo, X. Peng, M. Manley, Y.-C. Luo, S. Yu and M. S. Bakir, "3-D Heterogeneous Integration of RRAM-Based Compute-In-Memory: Impact of Integration Parameters on Inference Accuracy," in IEEE Transactions on Electron Devices (TED), doi: 10.1109/TED.2022.3231570.

  2. T. Zheng and M. S. Bakir, "Benchmarking Frequency-Dependent Parasitics of Fine-Pitch Off-Chip I/Os for 2.5D and 3D Heterogeneous Integration," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 12, pp. 2002-2012, Dec. 2022.

  3. S. Yu, T. K. Gaylord and M. S. Bakir, "Fiber-Array-to-Chip Interconnections With Sub-Micron Placement Accuracy via Self-Aligning Chiplets," in IEEE Photonics Technology Letters, vol. 34, no. 19, pp. 1023-1025, 1 Oct. 2022.

  4. J. Lu, M. Zia, M. J. Williams, A. L. Jacob, B. Chung, S. J. Sober and M. S. Bakir, "High-performance Flexible Microelectrode Array with PEDOT:PSS Coated 3D Micro-cones for Electromyographic Recording", in 44th International Engineering in Medicine and Biology Conference, Glasgow, United Kingdom, Jul. 2022.

  5. T. Zheng and M. S. Bakir, “Fused-Silica Stitch-Chips with Compressible Microinterconnects for Embedded RF/mm-wave Chiplets”, in 2022 IEEE/MTT-S International Microwave Symposium (IMS), Denver, CO, Jun. 2022.

  6. S. Kochupurackal Rajan, B. Ramakrishnan, H. Alissa, W. Kim, C. Belady and M. S. Bakir, "Integrated Silicon Microfluidic Cooling of a High-Power Overclocked CPU for Efficient Thermal Management," in IEEE Access, vol. 10, pp. 59259-59269, 2022, doi: 10.1109/ACCESS.2022.3179387.

  7. M. Manley, A. Kaul, M. -J. Li and M. S. Bakir, "Ultra-Dense 3D Polylithic Integration Technology", Government Microcircuit Applications & Critical Technology Conf., Miami, FL, Mar. 2022.

  8. J. R. Brescia, J. L. Gonzalez, T. Zheng and M. S. Bakir, "Replaceable Integrated Chiplet (PINCH) Assembly for Heterogeneous Integration", Government Microcircuit Applications & Critical Technology Conf., Miami, FL, Mar. 2022.

  9. T. Zheng, A. Kaul, S. Kochupurackal Rajan, and M. S. Bakir, "Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations," in B. Keser, and S. Kröhnert (Ed.), Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces (pp. 261-287) Wiley, 2021.

  10. M. -J. Li and M. S. Bakir, "3-D Integrated Chiplet Encapsulation (3-D ICE): High-Density Heterogeneous Integration Using SiO2-Reconstituted Tiers," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 12, pp. 2242-2245, Dec. 2021.

  11. J. L. Gonzalez, J. R. Brescia, T. Zheng, S. Kochupurackal Rajan and M. S. Bakir, "A Die-Level, Replaceable Integrated Chiplet (PINCH) Assembly Using a Socketed Platform, Compressible MicroInterconnects, and Self-Alignment," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 12, pp. 2069-2076, Dec. 2021.

  12. J. L. Gonzalez, S. Kochupurackal Rajan, J. R. Brescia and M. S. Bakir, "A Substrate-Agnostic, Submicrometer PSAS-to-PSAS Self-Alignment Technology for Heterogeneous Integration," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 12, pp. 2061-2068, Dec. 2021.

  13. Y. Wang, C. Swank, T. Zheng, J. F. Buckwalter, A. Kummel, M. Rodwell and M. S. Bakir, “Interposer and Advanced Packaging Enabled by Ultra-Dense Microdiamond Composites for RF/mm-wave Applications”, in Proceeding of TECHCON 2021, Sep. 2021.

  14. X. Peng, A. Kaul, M. S. Bakir and S. Yu, "Heterogeneous 3-D Integration of Multitier Compute-in-Memory Accelerators: An Electrical-Thermal Co-Design," in IEEE Transactions on Electron Devices, vol. 68, no. 11, pp. 5598-5605, Nov. 2021.

  15. T. Zheng, P. K. Jo, S. Kochupurackal Rajan and M. S. Bakir, "Electrical Characterization and Benchmarking of Polylithic Integration Using Fused-Silica Stitch-Chips With Compressible Microinterconnects for RF/mm-Wave Applications," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 11, pp. 1824-1834, Nov. 2021.

  16. Y. Hu, M. O. Hossen, Z. Wan, M.S. Bakir, and Y. Joshi, "Compact Transient Thermal Model of Microfluidically Cooled Three-Dimensional Stacked Chips With Pin-Fin Enhanced Microgap," in ASME. J. Electron. Packag., 143(3): 031007, Sep. 2021.

  17. R. Saligram, A. Kaul, M. S. Bakir, and A. Raychowdhury, “Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication,” in A. Calimera, P.-E. Gaillardon, K. Korgaonkar, S. Kvatinsky, R. Reis (Ed.), VLSI-SoC: Design Trends, (1st ed., pp. 149–178) Springer Cham, 2021.

  18. S. Kochupurackal Rajan, A. Kaul, T Sarvey, G. S. May, and M. S. Bakir, "Design Considerations, Demonstration, and Benchmarking of Silicon Micro-cold Plate and Monolithic Microfluidic Cooling for 2.5D ICs," 71st IEEE Electronic Components and Technology Conf. (ECTC),  Jun. 2021.

  19. P. Yeon, S. Kochupurackal Rajan, et al., "Microfabrication, Coil Characterization, and Hermetic Packaging of Millimeter-Sized Free-Floating Neural Probes," in IEEE Sensors Journal, vol. 21, no. 12, pp. 13837-13848, 15 June, 2021.

  20. S. Kochupurackal Rajan, A. Kaul, T. E. Sarvey, G. S. May and M. S. Bakir, "Monolithic Microfluidic Cooling of a Heterogeneous 2.5-D FPGA With Low-Profile 3-D Printed Manifolds," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 6, pp. 974-982, June 2021.

  21. X. Peng , W. Chakraborty, A. Kaul, W. Shim, M.S. Bakir, S. Datta, S. Yu, "Benchmarking Monolithic 3D Integration for Compute-in-Memory Accelerators: Overcoming ADC Bottlenecks and Maintaining Scalability to 7nm or Beyond," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2020.

  22. A. Kaul, X. Peng, S. Kochupurackal Rajan, S. Yu, and M.S. Bakir, "Thermal Modeling of 3D Polylithic Integration and Implications on BEOL RRAM Performance," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2020. (invited)

  23. M. -J. Li et al., "Cu–Cu Bonding Using Selective Cobalt Atomic Layer Deposition for 2.5-D/3-D Chip Integration Technologies," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 12, pp. 2125-2128, Dec. 2020.

  24. R. Saligram, A. Kaul, A. Raychowdhury, and M.S. Bakir, "A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration," in Proc. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), virtual, Salt Lake City, UT, Oct. 2020.

  25. P. Jo, S. Kochupurackal Rajan, J. Gonzalez and M. S. Bakir, "Polylithic Integration of 2.5-D and 3-D Chiplets Enabled by Multi-Height and Fine-Pitch CMIs,"  in IEEE Transactions on Components, Packaging and Manufacturing Technology, Jul.2020.

  26. H. Oh, M. Swaminathan, G. S. May and M. S. Bakir, "Electrical Circuit Modeling and Validation of Through-Silicon Vias Embedded in a Silicon Microfluidic Pin-Fin Heat Sink Filled With Deionized Water," in IEEE Trans. on Comp., Pack. and Manuf. Tech., Aug. 2020.

  27. T. Zheng, P. K. Jo, S. Kochupurackal Rajan, and M. S. Bakir, "Polylithic integration for RF/mm-wave chiplets using stitch-chips: modeling, fabrication, and characterization," 2020 IEEE MTT-S International Microwave Symposium (IMS), Los Angeles, CA, Jun. 2020.

  28. A. Kaul, S. Kochupurackal Rajan, M. O. Hossen, G. S. May, and M. S. Bakir, "BEOL-Embedded 3D Polylithic Integration: Thermal and Interconnection Considerations," 70th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2020.

  29. J. L. Gonzalez, T. Zheng, S. Kochupurackal Rajan, and M. S. Bakir, “Package Testing using a Socketed Heterogeneous 2.5D/3D Integration Module (SHIM) for mm-wave Applications,” Proceedings of the 2020 GOMAC-Tech – Government Microcircuit Applications and Critical Technology Conference, 2020.

  30. M. Zia, B. Chung, S. Sober, M. S. Bakir, "Flexible Multielectrode Arrays With 2-D and 3-D Contacts for In Vivo Electromyography Recording," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 2, pp. 197-202, Feb. 2020.

  31. M. O. Hossen, B. Chava, G. Van der Plas, E. Beyne and M. S. Bakir, "Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and  μ TSVs," in IEEE Trans. on Electron Devices, Jan. 2020.

  32. S. Kochupurackal Rajan, M. Li, G.S. May, and M.S. Bakir, "High density and low-temperature interconnection enabled by mechanical self-alignment and electroless plating" in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Sendai, Japan, Oct. 2019.

  33. T. E. Sarvey, A. Kaul, S. K. Rajan, A. Dasu, R. Gutala, and M. S. Bakir, "Microfluidic Cooling of a 14-nm 2.5-D FPGA With 3-D Printed Manifolds for High-Density Computing: Design Considerations, Fabrication, and Electrical Characterization," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 12, pp. 2393-2403, 2019.

  34. Y. Zhang, M. O. Hossen, and M. S. Bakir, "Power delivery network modeling and benchmarking for emerging heterogeneous integration technologies," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 9, pp. 1825-1834, 2019.

  35. C. Wan, J. L. Gonzalez, T. Fan, A. Adibi, T. K. Gaylord, and M. S. Bakir, "Fiber-Interconnect Silicon Chiplet Technology for Self-Aligned Fiber-to-Chip Assembly," IEEE Photonics Technology Letters, vol. 31, no. 16, pp. 1311-1314, 2019.

  36. P. K. Jo, T. Zheng, and M. S. Bakir, "Polylithic Integration of 2.5D and 3D Chiplets Using Interconnect Stitching," in Proc. 69th IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May. 2019.

  37. M. Zia, B. Chung, S. J. Sober and M.S. Bakir, "Fabrication and Characterization of 3D Multi-Electrode Array on Flexible Substrate for In Vivo EMG Recording from Expiratory Muscle of Songbird," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2018.

  38. Y. Zhang, X. Zhang, and M. S. Bakir, "Benchmarking Digital Die-to-Die Channels in 2.5-D and 3-D Heterogeneous Integration Platforms," IEEE Transactions on Electron Devices, vol. 65, no. 12, pp. 5460-5467, 2018.

  39. M. O. Hossen, J. L. Gonzalez, and M. S. Bakir, "Thermomechanical Analysis and Package-Level Optimization of Mechanically Flexible Interconnects for Interposer-on-Motherboard Assembly," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 8, no. 12, pp. 2081-2089, 2018.

  40. P. K. Jo, T. Zheng, and M. S. Bakir, "Multi-Die Polylithic Integration Enabled by Heterogeneous Interconnect Stitching Technology (HIST)," in 27th IEEE Conf. on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, Oct. 2018.

  41. M. O. Hossen, Y. Zhang, and M. Bakir, "Thermal-Power Delivery Network Co-analysis for Multi-Die Integration", in 27th IEEE Conf. on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, Oct. 2018.

  42. J. L. Gonzalez, P. K. Jo, R. Abbaspour, and M. S. Bakir, "A Disposable and Self-Aligned 3-D Integrated Bio-Sensing Interface Module for CMOS Cell-Based Biosensor Applications," IEEE Electron Device Letters, vol. 39, no. 8, pp. 1215-1218, 2018.

  43. M. Zia, H. Oh, and M. S. Bakir, "Post-CMOS Fabrication Technology Enabling Simultaneous Fabrication of 3-D Solenoidal Micro-Inductors and Flexible I/Os," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 8, no. 11, pp. 2039-2044, 2018.

  44. P. K. Jo, M. O. Hossen, X. Zhang, Y. Zhang, and M. S. Bakir, "Heterogeneous Multi-Die Stitching: Technology Demonstration and Design Considerations," in Proc. 68th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May. 2018.

  45. P. Asrar, X. Zhang, C. E. Green, M. S. Bakir, Y. K. Joshi, "Flow boiling of R245fa in a microgap with staggered circular cylindrical pin fins," Inter. Jour. of Heat and Mass Transfer, Volume 121, Pages 329-342, 2018.

  46. C. Wan, T. K. Gaylord, and M. S. Bakir, "Grating-assisted-cylindrical-resonant-cavities interlayer coupler," Applied Optics, vol. 57, no. 18, pp. 5079-5089, June 2018.

  47. P. K. Jo, X. Zhang, J. L. Gonzalez, G. S. May, and M. Bakir, "Heterogeneous Multi-Die Stitching Enabled by Fine-Pitch & Multi-Height Compressible MicroInterconnects (CMIs)," IEEE Transactions on Electron Devices, vol. 65, no. 7, pp. 2957-2963, July. 2018.

  48. J. L. Gonzalez, P. K. Jo, R. Abbaspour, and M. S. Bakir, "Flexible Interconnect Design using a Mechanically-focused, Multi-Objective Genetic Algorithm," IEEE Journal of Microelectromechanical Systems, vol. 27, no. 4, pp. 677-685, Aug. 2018.

  49.  P. Yeon, J. L. Gonzalez, M. Zia, S. Kochupurackal Rajan, G. S. May, M. S. Bakir, and M. Ghovanloo, "Microfabrication, Assembly, and Hermetic Packaging of mm-Sized Free-Floating Neural Probes," in Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, Oct. 2017.

  50.  P. K. Jo, M. Zia, J. L. Gonzalez, and M. S. Bakir, "Dense and highly elastic compressible microinterconnects (CMIs) for electronic microsystems," in Proc. 67th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May. 2017.

  51. P. K. Jo, M. Zia, J. L. Gonzalez, H. Oh, and M. S. Bakir, "Design, fabrication, and characterization of dense compressible microinterconnects,"IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 7, pp. 1003-1010, May. 2017.

  52. T. E. Sarvey, Y. Zhang, C. Cheung, R. Gutala. A. Rahman, A. Dasu, and M. S. Bakir, "Monolithic integration of a micropin-fin heat sink in a 28 nm FPGA," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 9, pp. 1465-1475, Sep. 2017.

  53. T. E. Sarvey, Y. Hu, C. E. Green, P. A. Kottke, D. C. Woodrum, Y. K. Joshi, A. G. Fedorov, S. K. Sitaraman, and M. S. Bakir, "Integrated circuit cooling using heterogeneous micropin-fin arrays for nonuniform power maps," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 10, pp. 1617-1624, Oct.2017

  54. M. H. Nasr, C. E. Green, P. A. Kottke, X. Zhang, T. E. Sarvey, Y. K. Joshi, M. S. Bakir, A. G. Fedorov, "Flow regimes and convective heat transfer of refrigerant flow boiling in ultra-small clearance microgaps," Inter. Jour. of Heat and Mass Transfer, Volume 108, Part B, Pages 1702-1713, 2017.

  55. Y. Zhang, T. E. Sarvey, and M. S. Bakir, "Thermal evaluation of 2.5-D integration using bridge-chip technology challenges and opportunities", IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 7, pp. 1101 - 1110, July 2017.

  56. Y. Zhang, M. O. Hossen, and M. S. Bakir, "Power Delivery Network Benchmarking For Interposer and Bridge-chip Based 2.5-D Integration," in IEEE Electron Device Letters, vol. 39, no. 1, pp. 99-102, Dec. 2017

  57. R. Abbaspour, D. K. Brown, and M. S. Bakir, "Fabrication and electrical characterization of sub-micron diameter through-silicon via for heterogeneous three-dimensional integrated circuits," Journal of Micromechanics and Microengineering, vol. 27, no. 2, pp. 025011-1-025011-8, Jan. 2017.

  58. C. Zhang, H. S. Yang, and M. S. Bakir, "A double-lithography and double-reflow process and application to multi-pitch multi-height mechanical flexible interconnects," Journal of Micromechanics and Microengineering, vol. 27, no. 2, pp. 025014-1-025014-6, Jan. 2017.

  59. X. Zhang, P. K. Jo, M. Zia, G. May, and M. S. Bakir, "Heterogeneous interconnect stitching technology with compressible microinterconnects for dense multi-die integration," IEEE Electron Device Letters, vol. 38, no. 2, pp. 255-257, Feb. 2017.

  60. C. Wan, T. K. Gaylord, and M. S. Bakir, "Circular waveguide grating-via-grating for interlayer coupling," IEEE Photonics Technology Letters, vol. 29, no. 21, pp. 1776-1779, Nov. 2017.

  61. Y. Zhang and M. S. Bakir, "Integrated thermal and power delivery network co-simulation framework for single-die and multi-die assemblies", IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 7, no. 3, pp. 434-443, Feb. 2017.

  62. J. C. Ciciliano, R. Abbaspour, J. Woodall, C. Wu, M. S. Bakir, and W. A. Lam, "Probing blood cell mechanics of hematologic processes at the single micron level," Lab on a Chip, vol. 17, no. 22, pp. 3804-3816, Nov. 2017.

  63.  H. Oh, X. Zhang, P. K. Jo, G. S. May, and M. S. Bakir, "Monolithic-like heterogeneously integrated microsystems using dense low-loss interconnects," in Proc. IEEE Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Phoenix, AZ, Jan. 2017. (invited).

  64. H. Oh, G. May, and M. Bakir, "Heterogeneous integrated microsystems with non-traditional through-silicon via technologies," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 7, no. 4, pp. 502-510, Mar. 2017.

  65. M.Zia, C.Wan, Y. Zhang and M.S. Bakir, “Electrical and photonic off-chip interconnection and system integration,” in Tolga Tekin, Nikos Pleros, Richard Pitwon, and Andreas Hakansson (Ed.), “Optical Interconnects for Data Centers,” (1st Edition p.265-286), Woodhead Publishing, Nov. 2016

  66. V. Kumar, H. Oh, X. Zhang, L. Zheng, M. S. Bakir, and A. Naeemi, "Impact of on-chip interconnect on the performance of 3D integrated circuits with through silicon vias Part I," IEEE Transaction on Electron Devices, vol. 63, no. 6, pp. 2503-2509, June 2016

  67. Y. Zhang, X. Zhang, W. Wahby, and M. S. Bakir, "Design considerations for 2.5-D and 3-D integration accounting for thermal constraints," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Nov. 2016.

  68.  W. Wahby, T. E. Sarvey, H. Sharma, H. Esmaeilzadeh, and M. S. Bakir, "The impact of 3D stacking on GPU-accelerated deep neural networks an experimental study," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Nov. 2016.

  69.  C. Wan, T. K. Gaylord, and M. S. Bakir, "Grating design for 3-D interconnections of waveguides in overlaid chips using the RCWA-EIS method," in Frontiers in Optics, Rochester, NY, Oct. 2016.

  70. X. Zhang, V. Kumar, H. Oh, L. Zheng, G. May, A. Naeemi, and M. S. Bakir, "Impact of on-chip interconnect on the performance of 3D integrated circuits with through silicon vias Part II," IEEE Transactions on Electron Devices, vol. 63, no. 6, pp. 2510-2516, June 2016

  71. W. Wahby and M. S. Bakir, "Impact of Alternate Metals on Routing in Scaled Monolithic 3DICs," in Proc. SRC Techcon, Austin, TX, Sep. 2016.

  72. D. Lorenzini, C. Green, T. E. Sarvey, X. Zhang, Y. Hu, A. G. Fedorov, M. S. Bakir, Y. Joshi, "Embedded single phase microfluidic thermal management for non-uniform heating and hotspots using microgaps with variable pin fin clustering," Inter. Jour. of Heat and Mass Transfer, Volume 103, Pages 1359-1370, 2016.

  73. P. Asrar, X. Zhang, C. E. Green, P. A. Kottke, T. E. Sarvey, A. G. Fedorov, M. S. Bakir, and Y. K. Joshi, "Flow boiling of R245fa in a microgap with integrated staggered pin fins," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  74. H. Oh, X. Zhang, G. May, and M. Bakir, "High-frequency analysis of embedded microfluidic cooling within 3-D ICs using a TSV testbed," in Proc. 66th IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May. 2016.

  75. M. H. Nasr, C. E. Green, P. E. Kottke, X. Zhang, T. E. Sarvey, Y. K. Joshi, M. S. Bakir, A. G. Fedorov, "Extreme-microgap based hotspot thermal management with refrigerant flow boiling," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  76. R. Abbaspour, D. C. Woodrum, P. A. Kottke, T. E. Sarvey, C. E. Green, Y. K. Joshi, A. G. Fedorov, S. K. Sitaraman, and M. S. Bakir, "Combined finned microgap with dedicated extreme-microgap hotspot flow for high performance thermal management," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  77. X. Zhang,  M. H. Nasr, D. C. Woodrum, C. E. Green, P. A. Kottke, T. E. Sarvey, Y. K. Joshi, S. K. Sitaraman, A. G. Fedorov, and M. S. Bakir, "Design, microfabrication and thermal characterization of the hotspot cooler testbed for convective boiling experiments in extreme-micro-gap with integrated micropin-fins and heat Loss minimization," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  78. P. Asrar, X. Zhang, C. E. Green, P. A. Kottke, T. E. Sarvey, A. G. Fedorov, M. S. Bakir, Y. K. Joshi, "Flow visualization of two phase flow of R245fa in a microgap with integrated staggered pin fins," in Thermal Measurement, Modeling & Management Symposium (SEMI-THERM), San Jose, CA, Mar. 2016.

  79. D. C. Woodrum, X. Zhang, P. A. Kottke, Y. K. Joshi, A. G. Fedorov, M. S. Bakir, and S. K. Sitaraman, "Reliability assessment of hydrofoil-shaped micro-pin fins subjected to high performance coolant," in IEEE The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  80. Y. Song, R. Abbaspour, M. S. Bakir, and S. K. Sitaraman, "Thermal annealing effects on copper microstructure in Through-Silicon-Vias," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  81. Y. Zhang, T. E. Sarvey, Y. Zhang, M. Zia and M. S. Bakir, "Numerical and experimental exploration of thermal isolation in 3D systems using air gap and mechanically flexible interconnects," in IEEE International Interconnect Technology Conf. / Advanced Metallization Conf. (IITC/AMC), San Jose, CA, May. 2016.

  82. P. Thadesar and M. S. Bakir, "Fabrication and characterization of polymer-enhanced TSVs, inductors and antennas for mixed-signal silicon interposer platforms," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6, no. 3, pp. 455-463, Mar. 2016.

  83. M. Zia, C. Zhang, H.S. Yang, L. Zheng and Muhannad Bakir, "Chip-to-chip interconnect integration technologies," IEICE Electron. Express, vol. 13, no. 6, pp. 1-16, Mar. 2016.

  84. H. Oh, P. A. Thadesar, G. S. May, and M. S. Bakir, "Low-Loss Air-Isolated Through-Silicon Vias for Silicon Interposers," IEEE Microw. Wirel. Components Lett., vol. 26, no. 3, pp. 168-170, Mar. 2016.

  85. H. Oh, G. May, and M. Bakir, "Analysis of signal propagation through TSVs within distilled water for liquid-cooled microsystems," IEEE Transaction Electron Devices, vol. 63, no. 3, pp. 1176-1181, Mar. 2016.

  86. X. Zhang, X. Han, T. E. Sarvey, C. E. Green, P. A. Kottke, A. G. Fedorov, Y. Joshi, and M. S. Bakir, "3D IC with embedded microfluidic cooling technology, thermal performance, and electrical implications," ASME Journal of Electronic Packaging, vol. 138, pp. 1-6, Mar. 2016.

  87. L. Zheng, Y. Zhang, and M. Bakir, "Full-Chip Power Supply Noise Time-Domain Numerical Modeling and Analysis for Single and Stacked ICs," IEEE Transaction on Electron Devices, vol. 63, no. 3, pp. 1225-1231, Mar. 2016.

  88. W. Wahby, L. Zheng, Y. Zhang, M. S. Bakir, "A simulation tool for rapid investigation of trends in 3DIC performance and power consumption," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no. 2, pp. 192-199, Feb. 2016.

  89. H. S. Yang, C. Zhang, and M. S. Bakir, "A self-aligning flip-chip assembly method using sacrificial positive self-alignment structures," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6, no. 3, pp. 471-477, Feb. 2016.

  90. M. Zia, T. Chi, J. Park, A. Su, J. L. Gonzalez, P. K. Jo, M. P. Styczynski, H. Wang, and M. S. Bakir, "A 3D integrated electronic microplate platform for lowcost repeatable biosensing applications," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6, no. 12, pp. 1827-1833, Dec. 2016.

  91. C. Wan, T. K. Gaylord, and M. S. Bakir, "Rigorous coupled-wave analysis equivalent-index-slab method for analyzing 3D angular misalignment in interlayer grating couplers," Applied Optics, vol. 55, no.35, pp. 10006-10015, Dec. 2016.

  92. J. Ciciliano, R. Abbaspour, C. Wu, M. S. Bakir, and W. A. Lam, "A microengineered matrix to decouple the biophysical and biochemical mechanisms of blood cell interactions with thrombi and vascular wall matrices," Blood Journal by American Society of Hematology, vol. 128, no. 22, p. 555, Dec. 2016.

  93. X. Liu, P. Thadesar, C. Taylor, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "Experimental stress characterization and numerical simulation for copper pumping analysis of through silicon vias (Invited)," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6, no. 7, pp. 993-999, July 2016

  94. P. Thadesar, X. Gu, R. Alapati and M. S. Bakir, "TSVs: Drivers, performance and innovations (Invited)," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no. 3, pp. 455-463, July 2016.

  95. C. Wan, T. K. Gaylord, and M. S. Bakir, "RCWA-EIS method for interlayer grating coupling," Applied Optics, vol. 55, no. 22, pp. 5900-5908, Aug. 2016.

  96. C. Wan, T. K. Gaylord, and M. S. Bakir, "Grating design for interlayer optical interconnection of in-plane waveguides," Applied Optics, vol. 55, no.10, pp. 2601-2610, Oct. 2016.

  97. C. Zhang, H. S. Yang, H. D. Thacker, I. Shubin, J. E. Cunningham, and M. S. Bakir, "Mechanically flexible interconnects with contact tip for rematable heterogeneous system integration," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6, no. 11, pp. 1587-1594, Oct. 2016.

  98. Y. Zhang, Y. Zhang, T. E. Sarvey, C. Zhang, M. Zia, M. S. Bakir, "Thermal isolation using air gap and mechanically flexible interconnects for heterogeneous 3D ICs," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6. no. 1, pp. 31-39, Dec. 2015.

  99. C. Green, P. Kottke, X. Han, C. Woodrum, T. E. Sarvey, P. Asrar, X. Zhang, Y. Joshi, A. Fedorov, S. Sitaraman, M. S. Bakir, "A review of two-phase forced cooling in three-dimensional stacked electronics: technology integration," ASME Journal of Electronic Packaging, vol 137, pp. 1-9, Dec. 2015.

  100. H. Oh, Y. Zhang, L. Zheng, G. S. May, and M. S. Bakir, "Fabrication and characterization of electrical interconnects and microfluidic cooling for 3D ICs with silicon interposer," Heat Transf. Eng., vol. 7632, pp. 1-41, Dec. 2015 (Invited).

  101.  M. Zia, T. Chi, C. Zhang, P. Thadesar, T. Hookway, J. Gonzalez, T. McDevitt, H. Wang, and M. S. Bakir, "A microfabricated electronic microplate platform for low-cost repeatable bio-sensing applications," in Proc. IEEE International Electron Devices Meeting (IEDM), Washington, DC, Dec. 2015.

  102. L. Zheng, Y. Zhang, and M. Bakir, "A Silicon interposer platform utilizing microfluidic cooling for high-performance computing systems," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 5, pp. 1379-1386, Oct. 2015.

  103. . M. Zia, C. Zhang, P. Thadesar, T. Hookway, T. Chi, J. Gonzalez, T. McDevitt, H. Wang,  and M. S. Bakir, "Fabrication of and cell growth on silicon membranes with high density TSVs for bio-sensing applications," in Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), Atlanta, GA, Oct. 2015.

  104. T. E. Sarvey, Y. Zhang, L. Zheng, P. Thadesar, R. Gutala, C. Cheung, A. Rahman, M. S. Bakir, "Embedded cooling technologies for densely integrated electronic systems," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Oct. 2015. (invited)

  105. X. Zhang, V. Kumar, R. Alapati, A. Naeemi and M. S. Bakir, "Interconnect performance in 3D ICs accounting TSV frequency-dependent capacitance and resistive on-chip wires: model, fabrication, and testing," in Proc. SRC Techcon, Austin, TX, Sep. 2015.

  106. . H. Oh, G. May, and M. Bakir, "Silicon interposer platform with low-loss through-silicon vias using air," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Sendai, Japan, Aug. 2015.

  107. . X. Zhang, X. Han, T. E. Sarvey, C. E. Green, P. A. Kottke, A. G. Fedorov, Y. Joshi, and M. S. Bakir, "3D IC with embedded microfluidic cooling: technology, thermal performance, and electrical implications," in Proc. Int. Tech. Conf. and Expo. Packaging and Integration of Electronic and Photonic Microsystems and Int. Conf. Nanochannels, Microchannels, and Minichannels (InterPACKICNMM), San Francisco, CA, July 2015.

  108. H. Oh, J. M. Gu, S. J. Hong, G. S. May, and M. S. Bakir, "High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems," Microelectronic Engineering, vol. 142, pp. 30-35, July 2015.

  109. C. E. Green, P. E. Kottke, T. E. Sarvey, A. G. Federov, Y. Joshi, M. S. Bakir, "Performance and integration implications of addressing localized hotspots through two approaches: clustering of micro pin-fins and dedicated microgap coolers," in Proc. Int. Tech. Conf. and Expo. Packaging and Integration of Electronic and Photonic Microsystems and Int. Conf. Nanochannels, Microchannels, and Minichannels (InterPACKICNMM), San Francisco, CA, July 2015.

  110. D. C. Woodrum, T. Sarvey, M. S. Bakir and S. K. Sitaraman, "Reliability study of micro-pin fin array for on-chip cooling," in Proc. 65th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 2015.

  111. L. Zheng, Y. Zhang, X. Zhang, and M. Bakir, "Silicon interposer with embedded microfluidic cooling for high-performance computing systems," in Proc. 65th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 2015.

  112. P. Thadesar and M. Bakir, "Fabrication and characterization of mixed-signal polymer-enhanced silicon interposer featuring photodefined coax TSVs and high-Q inductors," in Proc. 65th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 2015.

  113. C. Zhang, P. Thadesar, M. Zia, T. E. Sarvey, and M. S. Bakir, "Au-NiW mechanically flexible interconnects (MFIs) for rematable 3D integration," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Cork, Ireland, Dec. 2014.

  114. Y. Zhang, Y. Zhang, M. S. Bakir, "Thermal design and constraints for heterogeneous integrated chip stacks and isolation technology using air gap and thermal bridge," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol.4, no.12, pp.1914-1924, Dec. 2014.

  115. Y. Zhang, T. E. Sarvey, and M. S. Bakir, "Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Cork, Ireland, Dec. 2014.

  116. H. S. Yang, C. Zhang, and M. Bakir, "Self-aligned silicon interposer tiles and silicon bridges using positive self-alignment structures and rematable mechanically flexible interconnects", IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 4, no. 11, pp. 1760-1768, Nov. 2014.

  117. X. Liu, P. Thadesar, C. Taylor, H. Oh, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "In-situ microscale through-silicon via strain measurements by synchrotron x-ray microdiffraction exploring the physics behind data interpretation," Applied Physics Letters, vol.105, no.11, p.112109, Sep. 2014.

  118. H. S. Yang, C. Zhang, and M. Bakir, "Self-aligning silicon interposer tiles and silicon bridges for large nanophotonics enabled systems", Electronics Letters, vol. 50, no. 20, pp. 1475-1477, Sep. 2014.

  119. W. Wahby, L. Zheng, Y. Zhang, and M. Bakir, "A virtual integration platform for 3DIC design space exploration," in Proc. SRC Techcon, Austin, TX, Sep. 2014.

  120. H. Oh, Y. Zhang, L. Zheng, and M. Bakir,"Electrical interconnect and microfluidic cooling within 3D ICs and silicon interposer," in Proc. Int. Tech. Conf. and Expo. Packaging and Integration of Electronic and Photonic Microsystems and Int. Conf. Nanochannels, Microchannels, and Minichannels (InterPACKICNMM), Chicago, IL, Aug. 2014.

  121. V. Kumar, R. Sharma, E. Uzunlar, L. Zheng, R. Bashirullah, P. Kohl, M. S. Bakir, and A. Naeemi, "Airgap interconnects: modeling, optimization, and benchmarking for backplane, PCB, and interposer applications," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol.4, no.8, pp.1335-1346, Aug. 2014.

  122. J. M. Gu, P. Thadesar, A. Dembla, M. S. Bakir, G. S. May, and S. J. Hong "Endpoint detection in low open area TSV fabrication using optical emission spectroscopy," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 4, no. 7, pp. 1251-1260, July 2014.

  123. P. Thadesar, L. Zheng, and M. Bakir, "Low-loss silicon interposer for three-dimensional system integration with embedded microfluidic cooling," in Proc. IEEE VLSI Technology Symposium, Honolulu, HI, June 2014.

  124. C. Zhang, H. S. Yang, and M. Bakir, "Mechanically flexible interconnects (MFIs) with highly scalable pitch," Journal of Micromechanics and Microengineering, vol. 24, no. 5, pp. 055024, May 2014.

  125. H. S. Yang, C. Zhang, M. Zia, L. Zheng, M. Bakir, "Interposer-to-interposer electrical and silicon photonic interconnection platform using silicon bridge," in Proc. IEEE Photonics Society Optical Interconnects Conf., Coronado, CA, May 2014.

  126. L. Zheng, Y. Zhang, and M. Bakir, "Novel electrical and fluidic microbumps for silicon interposer and 3D-ICs," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 4, no. 5, pp. 777-785, May 2014.

  127. T. E. Sarvey, Y. Zhang, Y. Zhang, H. Oh, and M. S. Bakir, "Thermal and electrical effects of staggered micropin-fin dimensions for cooling of 3D microsystems,"in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Orlando, FL, May 2014.

  128. C. Zhang, H.S. Yang, M. Bakir, "Mechanically flexible interconnects with highly scalable pitch and large stand-off height for silicon interposer tile and bridge interconnection," in Proc. 64th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2014.

  129. S. A. Isaacs, Y. Joshi, Y. Zhang, M. Bakir, and Y. J. Kim, "Two-phase flow and heat transfer in pin-fin enhanced micro-gaps with non-uniform heating," in Proc. ASME Int. Conf. on Micro/Nanoscale Heat and Mass Transfer, Hong Kong, China, Dec. 2013.

  130. Y. Zhang, A. Dembla, and M. S. Bakir, "Silicon micropin-fin heat sink with integrated TSVs for 3-D ICs: trade-off analysis and experimental testing," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 3, no. 11, pp. 1842-1850, Nov. 2013.

  131. Y. Zhang, L. Zheng, and M. S. Bakir, "3-D stacked tier-specific microfluidic cooling for heterogeneous 3-D ICs," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 3, no. 11, pp. 1811-1819, Nov. 2013.

  132. W. Wahby, A. Dembla, and M. Bakir, "Evaluation of 3DICs and fabrication of monolithic interlayer vias," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Oct. 2013.

  133. C. Zhang, H. S. Yang, and M. Bakir, "Highly elastic gold passivated mechanically flexible interconnects," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 3, no. 10, pp. 1632-1639, Oct. 2013.

  134. Y. Zhang, H. Oh, and M. Bakir, "Within-tier cooling and thermal isolation technologies for heterogeneous 3D ICs," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Oct. 2013.

  135. H. Oh, A. Dembla, Y. Zhang, and M. Bakir "High aspect ratio TSVs in micro-pinfin heat sinks for 3D ICs," in Proc. SRC TECHCON, Austin, TX, Sep. 2013.

  136. Best in Session Paper Award: P. Thadesar and M. Bakir "Fabrication and wideband characterization of novel photodefined polymer-embedded vias for silicon interposers," in Proc. SRC TECHCON, Austin, TX, Sep. 2013.

  137. X. Liu, P. Thadesar, C. Taylor, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "Dimension and liner dependent thermomechanical strain characterization of through-silicon vias using synchrotron x-ray diffraction," Journal of Applied Physics, vol. 114, no. 6, pp. 064908, Aug. 2013.

  138. P. Thadesar and M. Bakir, "Novel photo-defined polymer-enhanced through-silicon vias for silicon interposers," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 3, no. 7, pp. 1130-1137, July 2013.

  139. X. Liu, P. Thadesar, C. Taylor, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "Thermomechanical strain measurements by synchrotron x-ray diffraction and data interpretation for through-silicon vias," Applied Physics Letters , vol. 103, no. 2, pp. 022107-1-022107-5, July 2013.

  140. J. M. Gu, P. Thadesar, A. Dembla, S. J. Hong, M. S. Bakir, and G. May, "Endpoint detection using optical emission spectroscopy in TSV fabrication," in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  141. Y. Zhang, L. Zheng, and M. Bakir, "Tier-independent microfluidic cooling for heterogeneous 3D ICs with nonuniform power dissipation," in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  142. V. Kumar, L. Zheng, M. Bakir, and A. Naeemi, "Compact modeling and optimization of fine-pitch interconnects for silicon interposers", in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  143. P. Thadesar, A. Dembla, D. Brown, and M. S. Bakir, "Novel through-silicon via technologies for 3D system integration," in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  144. P. Thadesar, J. M. Gu, A. Dembla, S. J. Hong, G. S. May and M. S. Bakir, "Novel photodefined polymer-clad through-silicon via technology integrated with end point detection using optical emission spectroscopy," in Proc. 24th Annual SEMI Advanced Semiconductor Manufacturing Conf. (ASMC), Saratoga Springs, NY, May 2013.

  145. L. Zheng, Y. Zhang and M. Bakir, "Design, fabrication and assembly of novel electrical and microfluidic I/Os for 3-D chip stack and silicon interposer," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.

  146. H.S. Yang, C. Zhang, M.S. Bakir, "A low-cost self-alignment structures for heterogeneous 3D integration," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.

  147. P. Thadesar and M. Bakir, "Fabrication and characterization of novel photodefined polymer-enhanced through-silicon vias for silicon interposers," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.

  148. Y. Zhang and M. S. Bakir, "Independent interlayer microfluidic cooling for heterogeneous 3D IC applications," Electronics Letters, vol. 49, no. 6, pp. 404-406, Mar. 2013.

  149. P. Thadesar and M. Bakir, "Novel low-loss photodefined electrical TSVs for silicon interposers," Topical Workshop on Advanced 3D Packaging, 9th IMAPS Int. Conf. and Exhibition on Device Packaging, Scottsdale/Fountain Hills, AZ, Mar. 2013.

  150. H. S. Yang, P. Thadesar, C. Zhang, M.S. Bakir, (2013). Mechanically Flexible Interconnects and TSVs: Applications in CMOS/MEMS Integration. In V. Choudhary and K. Iniewski (Ed.), MEMS: Fundamental Technology and Applications (1st ed., p111-p130). FL, USA: CRC Press

  151. P. Thadesar and M. Bakir, "Novel photodefined polymer-embedded vias for silicon interposers," Journal of Micromechanics and Microengineering, vol. 23, no. 3, pp. 035003-1-035003-6, Mar. 2013.

  152. H. S. Yang, P. Thadesar, C. Zhang, M.S. Bakir, (2013). Mechanically Flexible Interconnects and TSVs: Applications in CMOS/MEMS Integration. In L. A. Francis and K. Iniewski (Ed.), Novel Advances in Microsystems Technologies and Their Applications (1st ed., p45-p68). FL, USA: CRC Press

  153. P. Thadesar and M. Bakir, "Silicon interposer featuring novel electrical and optical TSVs," in Proc. ASME International Mechanical Engineering Congress and Exposition, Houston, TX, Nov. 2012.

  154. A. Dembla, Y. Zhang, and M. Bakir, "Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs," in Proc. SRC TECHCON, Austin, TX, Sep. 2012.

  155. L. Zheng and M. Bakir, "Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer," in Proc. IEEE International System-on-Chip Conf. (SoCC), 2012.

  156. A. Dembla, Y. Zhang, and M. Bakir, "High aspect ratio TSVs in micropin-fin heat sinks for 3D ICs," in Proc. IEEE Int. Conf. Nanotechnology, Birmingham, England, Aug. 2012.

  157. S. A. Isaacs, Yoon Jo Kim, A. J. McNamara, Y. Joshi, Y. Zhang and M. S. Bakir, "Two-phase flow and heat transfer in pin-fin enhanced micro-gaps," 13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, San Diego, CA, 2012, pp. 1084-1089.

  158. A. Dembla, Y. Zhang, and M. Bakir, "Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs," in Proc. IEEE International Interconnect Technology Conf. (IITC), San Jose, CA, June 2012.

  159. C. Zhang, H. S. Yang, and M. Bakir, "Gold passivated mechanically flexible interconnects (MFIs) with high elastic deformation," in Proc. 62nd IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, 2012.

  160. Y. Zhang, A. Dembla, Y. Joshi, and M. Bakir, "3D stacked microfluidic cooling for high-performance 3D ICs" in Proc. 62nd IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, 2012.

  161. G. Huang, M. Bakir, A. Naeemi, and J. Meindl, "Power delivery for 3-D chip stacks: physical modeling and design implication," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 2, no. 5, pp. 852-859, May 2012.

  162. H. S. Yang, M. S. Bakir, "Design, fabrication, and characterization of freestanding mechanically flexible interconnects using curved sacrificial layer," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol.2, no.4, pp.561-568, Apr. 2012

  163. H. S. Yang, R. Ravindran, C. Zhang, P. Modarres, and M. Bakir, "Enabling technologies for 3D stacking of disposable electronic biosensor and CMOS Chips," Future Fab International, pp. 80-85, Oct. 2011. (invited)

  164. L. Zheng, G. Huang, and M. Bakir, "Power delivery and thermal management for high-performance 3D chip stack," in SRC Techcon, Austin, TX, Sep. 2011.

  165. A. Dembla, D. Brown, and M. Bakir, "Nanofabrication of ultra high density nanoscale TSVs," in SRC Techcon, Austin, TX, Sep. 2011.

  166. H. S. Yang and M. Bakir, "Design and wafer-level fabrication of positive self-alignment structures for improved vertical optical coupling," in IMAPS/IEEE-CPMT Advanced Technology Workshop on Optoelectronic Packaging, Irvine, CA, June 2011.

  167. A. Dembla, D. Brown, and M. Bakir, "Nanofabrication of high aspect ratio nanoscale TSVs," in Proc. Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), Las Vegas, NV, May. 2011.

  168. Y. Zhang, C. King, J. Zaveri, Y. J. Kim, V. Sahu, Y. Joshi, and M. Bakir, "Coupled electrical and thermal 3D IC centric microfluidic heat sink design and technology," in Proc. 61st IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2011.

  169. M. Parekh, P. Thadesar and M. Bakir, "Electrical, optical, and fluidic through-silicon vias for silicon interposer applications," in Proc. 61st IEEE Electronic Components and Technology Conf., Lake Buena Vista, FL, May 2011.

  170. M. Bakir, P. Thadesar, C. King, J. Zaveri, H. Yang, C. Zhang, Y. Zhang, "Revolutionary innovation in system interconnection: A new era for the IC," in Proc. Photonics West, Proc. of SPIE, Feb. 2011.

  171. H. S. Yang and M. Bakir, "3D integration of CMOS and MEMS using MFI and TSV," in Proc. SRC Techcon, 2010.

  172. Y. Zhang, J. Zaveri, C. King, and M. Bakir, "Coupled electrical and thermal 3D IC centric microfluid heat sink design," in Proc. SRC Techcon, 2010.

  173. H. S. Yang and M. Bakir, "3D integration of CMOS and MEMS using mechanically flexible interconnects (MFI) and through silicon vias (TSV)," in Proc. IEEE Electronic Components and Technol. Conf., pp. 822-828, 2010.

  174. R. Ravindran, J. A. Sadie, K. E. Scarberry, H. S. Yang, M. S. Bakir, J. F. McDonald, and J. D. Meindl, "Biochemical sensing with an arrayed silicon nanowire platform," in Proc. IEEE Electronic Components and Technol. Conf., pp. 1015-1020, 2010.

  175. H. S. Yang, R. Ravindran, M. S. Bakir, J.D. Meindl, "A 3D interconnect system for large biosensor array and CMOS signal-processing IC integration," IEEE Interconnect Technology Conf. (IITC), 2010 International, 6-9 June 2010

  176. C. King, J. Zaveri, M. Bakir, and J. Meindl, "Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs," in Proc. IEEE Electronic Components and Technology Conf., pp. 822-828, 2010.

  177. H. S. Yang and M. Bakir, "Interconnect technologies for 3D integration of CMOS and MEMS," in Proc. MRS Spring Meeting, 2010. (invited)

  178. B. Dang, M. Bakir, D. Sekar, and J. Meindl, "Single and 3D chip cooling using microchannels and microfluidic chip input/output (I/O) interconnects," IEEE Transaction on Advanced Packaging, vol. 3, no. 1, pp. 79-87, Feb. 2010.

  179. J.-H Lai, H. S. Yang, H. Chen, C. King, J. Zaveri, R. Ravindran, and M. Bakir, "A 'mesh' seed layer for improved through-silicon-via fabrication," Journal of Micromechanics and Microengineering, vol. 20, no. 2, pp. 025016-1-025016-6, Jan. 2010.

  180. M. Bakir, G. Huang, and B. Dang, "3D Integration: Limits and Opportunities," in Coupled Data Techniques, R. Ho and R. Drost (Eds.), Chapter 2, Springer, 2010.

  181. J. Zaveri, C. King Jr., H.S. Yang, M.S. Bakir, "Wafer level batch fabrication of silicon microchannel heat sinks and electrical through silicon vias for 3D ICs," IMAPS 42nd International Symposium on Microelectronics, 2009.

  182. C. King, J. Zaveri, H. S. Yang, M. Bakir, and J. Meindl "Electro-fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs," in Proc. SRC TECHCON, 2009.

  183. J. Zaveri, C. King, H. Yang, and M. Bakir, "Wafer level batch fabrication of silicon microchannel heat sinks and electrical through silicon vias" in Proc. SRC TECHCON, 2009.

  184. D. Sekar, C. King, B. Dang, M. Bakir, J. Meindl, "Removing heat from 3D stacked chips," Future Fab International, Vol. 29, no. 4, pp. 80-85, Apr. 2009. (invited)

  185. M. Bakir and J. Meindl (Eds.), "Integrated Interconnect Technologies for 3D Nanoelectronic Systems", Artech House, 2009. (16 chapters; 550-pages)

  186. M. Bakir and G. Huang, “Power Delivery, Signaling and Cooling for 3D Integrated Systems,” MRS Proceedings, vol. 1156, Jan. 2009.

  187. M. Bakir and J. Meindl, "Revolutionary Silicon Ancillary Technologies for the Next Era of Gigascale Integration," in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl (Eds.), Artech House 2009.

  188. B. Dang, M. Bakir, D. Sekar, C. King, and J. Meindl, "Single and 3D Chip Cooling using Microchannels and Fluidic I/Os," in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl (Eds.), Artech House 2009.

  189. G. Huang, K. Shakeri, A. Naeemi, M. Bakir, and J. Meindl, "On-Chip Power Supply Noise Modeling and Chip/Package Co-Design of Gigascale and 3D Integrations," in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl (Eds.), Artech House 2009.

  190. M. Bakir, G. Huang, D. Sekar, and C. King, "3D system integration: power delivery, cooling, and signaling," IETE Technical Review, vol. 26, no. 6, pp. 407-416, 2009. (invited)

  191. M. S. Bakir, C. King, D. Sekar, and B. Dang, “Electrical, optical, and fluidic interconnect networks for 3D heterogeneous integrated systems,” 2008 IEEE Avionics, Fiber-Optics and Photonics Technology Conference, Sep. 2008.

  192. M. S. Bakir, C. King, D. Sekar, H. Thacker, B. Dang, G. Huang, A. Naeemi, and J. D. Meindl, “3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation,” 2008 IEEE Custom Integrated Circuits Conference, Sep. 2008.

  193. Bakir, M.S., Sekar, D., Dang, B., King, C. and Meindl, J.D., Georgia Tech Research Corp, 2011. 3-D ICs with microfluidic interconnects and methods of constructing same. U.S. Patent 7,928,563.

  194. D. Sekar, C. King, B. Dang, T. Spencer, H. Thacker, P. Joseph, M. Bakir, and J. Meindl, “A 3D-IC Technology with Integrated Microchannel Cooling,” 2008 International Interconnect Technology Conference, Jun. 2008.

  195. C. King, D. Sekar, M. Bakir, B. Dang, J. Pikarsky, and J. Meindl, "3D stacking of chips with electrical and microfluidic I/O interconnects," in Proc. SRC TECHCON, 2008.

  196. C. R. King, D. Sekar, M. S. Bakir, B. Dang, J. Pikarsky, and J. D. Meindl, “3D stacking of chips with electrical and microfluidic I/O interconnects,” 2008 58th Electronic Components and Technology Conference, May 2008.

  197. M. Bakir, A. Glebov, M. Lee, P. Kohl, and J. Meindl, "Mechanically flexible chip-to-substrate optical interconnections using optical pillars," IEEE Transaction on Adv. Packaging, vol. 31, no. 1, pp. 143-153, Feb. 2008.

  198. G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. D. Meindl, “Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication,” 2007 IEEE Electrical Performance of Electronic Packaging, Oct. 2007.

  199. M. S. Bakir, B. Dang, and J. D. Meindl, “Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems,” 2007 IEEE Custom Integrated Circuits Conference, Sep. 2007.

  200. M. Bakir, B. Dang, O. Ogunsola, R. Sarvari, and J. Meindl, "Electrical and optical chip I/O interconnections for gigascale systems," IEEE Transaction on Electron Devices, vol. 54, no. 9, pp. 2426-2437, Sep. 2007.

  201. M. S. Bakir, B. Dang, and J. D. Meindl, “Electrical, Optical and Thermofluidic Chip I/O Interconnections,” ASME 2007 InterPACK Conference, Volume 1, Jul. 2007.

  202. M. Bakir, B. Dang, G. Huang, and J. Meindl, "Limits and opportunities for heat removal and power delivery to gigascale systems," in Proc. SEMATECH Thermal and Design Issues in 3D ICs, 2007. (invited) Paper featured in multiple trade journal articles.

  203. C. King, D. Sekar, M. Bakir, B. Dang, J. Pikarsky, J. Meindl, "Assembly techniques for microfluidic networks in three-dimensional integrated circuits," SRC TECHCON, 2007.

  204. M. Bakir and J. Meindl, "Fully compatible low cost electrical, optical, and fluidic I/O interconnect networks for ultimate performance 3D gigascale systems," in Proc. Int. 3D System-in-Chip Conf., 2007. (invited, Tokyo,  Japan)

  205. M. S. Bakir, B. Dang, O. O. Ogunsola, and J. D. Meindl, “‘trimoda’ Wafer-Level Package: Fully Compatible Electrical, Optical, and Fluidic Chip I/O Interconnects,” 2007 Proceedings 57th Electronic Components and Technology Conference, May 2007.

  206. M. S. Bakir, P. A. Kohl, A. L. Glebov, E. Elce, D. Bhusari, M. G. Lee, and J. D. Meindl, “Flexible polymer pillars for optical chip assembly: materials, structures, and characterization,” Photonics Packaging, Integration, and Interconnects VII, Feb. 2007.

  207. M. Bakir, "Nanoimprint Lithography for Semiconductor and Interconnect Technologies," in NanoTechnology: An Open Text, S. Campbell (Ed.), NSF NNIN 2007.

  208. H. Thacker, O. Ogunsola, A. Carson, M. Bakir, and J. Meindl, “Optical Through-Wafer Interconnects for 3D Hyper-Integration,” LEOS 2006 - 19th Annual Meeting of the IEEE Lasers and Electro-Optics Society, Oct. 2006.

  209. O. Ogunsola, H. D. Thacker, B. L. Bachim, M. S. Bakir, J. Pikarsky, T. K. Gaylord, and J. D. Meindl, "Chip-level waveguide-mirror-pillar optical interconnect structure," IEEE Photon. Technol. Lett., vol. 18, no. 15, pp. 1672-1674, Aug. 2006.

  210. O. Ogunsola, H. Thacker, B. Bachim, M. Bakir, T. Gaylord, and J. Meindl, “Polymer Pillars as Optical I/O for Gigascale Chips using Mirror-Terminated Waveguides,” 2006 International Interconnect Technology Conference, Jun. 2006.

  211. B. Dang, M. S. Bakir, C. S. Patel, H. D. Thacker, and J. D. Meindl, "Sea-of-Leads MEMS I/O interconnects for low-k IC packaging," IEEE J. Microelectromechanical Systems, vol. 15, no. 3, pp. 523-530, June 2006.

  212. K.-N. Chen, M. Bakir, J. Meindl, and R. Reif, "Copper interconnect bonding for polymer pillar I/O interconnects and three-dimensional (3D) integration applications," in Proc. TMS Electronics Materials Conf., 2006.

  213. M. S. Bakir, B. Dang, H. D. Thacker, O. O. Ogunsola, R. Ogra, and J. Meindl, “Dual-Mode Electrical-Optical Flip-Chip I/O Interconnects and a Compatible Probe Substrate for Wafer-Level Testing,” 56th Electronic Components and Technology Conference 2006, May 2006.

  214. A. He, M. S. Bakir, S. Ann, B. Allen, and P. Kohl, “Fabrication of Compliant, Copper-Based Chip-to-Substrate Connections,” 56th Electronic Components and Technology Conference 2006, May 2006.

  215. L. Glebov, D. Bhusari, P. Kohl, M. Bakir, J. Meindl, and M. G. Lee, "Flexible pillars for displacement compensation in optical chip assembly," IEEE. Photon. Technol. Lett., vol. 18, no. 6, pp. 974-976, Apr. 2006.

  216. B. Dang, M. S. Bakir, and J. D. Meindl, "Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink," IEEE Electron Device Letters, vol. 27, no. 2, pp. 117-119, Feb. 2006.

  217. B. Dang, P. Joseph, M. Bakir, P. Kohl, J. Meindl, "Fabrication, assembly and testing of an on-chip microfluidic heat sink," in Proc. Int. Symp. of Microelectronics, 2005, TP2:pp.1-5.

  218. M. S. Bakir, B. Dang, R. Emery, G. Vandentop, P. A. Kohl, and J. D. Meindl, "Sea of Leads compliant I/O interconnection process integration for the ultimate enabling of chips with low-k interlayer dielectrics," IEEE J. Adv. Packag., vol. 28, no. 3, pp. 488-494, Aug. 2005.

  219. B. Dang et al., "A Chip-Scale Cooling Scheme With Integrated Heat Sink and Thermal-Fluidic I/O Interconnects," in ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference, 2005, vol. Advances in Electronic Packaging, Parts A, B, and C, pp. 605-610, doi: 10.1115/ipack2005-73416.

  220. H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, “Probe Module for Wafer-Level Testing of Gigascale Chips With Electrical and Optical I/O Interconnects,” Advances in Electronic Packaging, Parts A, B, and C, Jul. 2005.

  221. B. Dang, P. J. Joseph, X. Wei, M. S. Bakir, P. A. Kohl, Y. K. Joshi, and J. D. Meindl, “A Chip-Scale Cooling Scheme With Integrated Heat Sink and Thermal-Fluidic I/O Interconnects,” in Proc. ASME InterPACK, Jul. 2005.

  222. H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, “High-density probe substrate for testing optical interconnects,” Proceedings of the IEEE 2005 International Interconnect Technology Conference, Jun. 2005.

  223. B. Dang, P. Joseph, M. Bakir, T. Spencer, P. Kohl, and J. Meindl, “Wafer-level microfluidic cooling interconnects for GSI,” Proceedings of the IEEE 2005 International Interconnect Technology Conference, Jun. 2005.

  224. H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, "Probe module for wafer-level testing of gigascale chips with polymer pillar-based electrical and optical I/O interconnects," in Proc. SRC TECHCON, 2005.

  225. B. Dang, P. J. Joseph, M. S. Bakir, P. A. Kohl, Y. K. Joshi, and J. D. Meindl, "A chip-scale cooling scheme with on-chip heat sink and integrated microfluidic I/O interconnects," in Proceedings SRC TECHCON, 2005.

  226. O. Ogunsola, H. Thacker, B. Bachim, M. Bakir, T. Gaylord, J. Meindl, "Mirror-enabled polymer pillar optical I/O interconnects for gigascale integration," in Proc. SRC TECHCON, 2005.

  227. M. Bakir, and J. D. Meindl, "Wafer-level packaging of optoelectronic chips using sea of leads electrical and optical I/O interconnections," in The 17th Annual Meeting of the IEEELasers and Electro-Optics Society, 2004: IEEE, pp. 583-584.

  228. B. Dang, M. Bakir, K. Martin, and J. Meindl, "Assembly and reliability assessment of Sea-of-Leads compliant wafer level package," in Proceedings IMAPS International Symposium on Microelectronics, 2004, pp 7-14.

  229. K. Shakeri, M. Bakir, and J. D. Meindl, "Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distribution," in IEEE International SOC Conference, 2004. Proceedings., 2004: IEEE, pp. 78-81.

  230. M. S. Bakir and J. D. Meindl, "Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration," IEEE Transaction Electron Devices, vol. 51, no. 7, pp. 1069-1077, July 2004.

  231. M. S. Bakir, C. O. Chui, A. K. Okyay, K. C. Saraswat, and J. D. Meindl, "Integration of optical polymer pillars chip I/O interconnections with Si MSM photodetectors," IEEE Transaction on Electron Devices, vol. 51, no. 7, pp. 1084-1090, July 2004.

  232. M. S. Bakir and J. D. Meindl, "Integrated electrical, optical, and thermal high density and compliant wafer-level chip I/O interconnections for gigascale integration," in 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No. 04CH37546), 2004, vol. 1: IEEE, pp. 1-6.

  233. B. Dang, C. Patel, H. Thacker, M. Bakir, K. Martin, and J. Meindl, "Optimal implementation of sea of leads (SoL) compliant interconnect technology," in Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No. 04TH8729), 2004: IEEE, pp. 99-101.

  234. M. S. Bakir et al., "Chip integration of sea of leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics," in 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No. 04CH37546), 2004, vol. 1: IEEE, pp. 1167-1173.

  235. M. S. Bakir, T. K. Gaylord, O. O. Ogunsola, E. G. Glytsis, and J. D. Meindl, "Optical transmission of polymer pillars for chip I/O optical interconnections," IEEE Photon. Technol. Lett., vol. 16, no. 1, pp. 117-119, Jan. 2004.

  236. M. S. Bakir, T. K. Gaylord, K. P. Martin, and J. D. Meindl, "Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections," IEEE Photon. Technol. Lett., vol. 15, no. 11, pp. 1567-1569, Nov. 2003.

  237. D. C. Keezer, C. S. Patel, M. S. Bakir, Q. Zhou, and J. D. Meindl, "Electrical test strategies for a wafer-level packaging technology," IEEE Trans. Electron. Packag. Manufac., vol. 26, no. 4, pp. 267-272, Oct. 2003.

  238. M. S. Bakir, H. A. Reed, H. D. Thacker, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)," IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2039-2048, Oct. 2003.

  239. M. S. Bakir et al., "Sea of polymer pillars: Dual-mode electrical-optical input/output interconnections," in Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No. 03TH8695), 2003: IEEE, pp. 77-79.

  240. M. S. Bakir, T. Gaylord, P. Kohl, K. Martin, and J. Meindl, "Sea of dual mode polymer pillar I/O interconnections for gigascale integration," in 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., 2003: IEEE, pp. 372-373.

  241. M. S. Bakir, H. A. Reed, A. V. Mule, J. Jayachandran, P. A. Kohl, T. K. Gaylord, K. P. Martin, and J. D. Meindl, "Chip-to-module interconnections using 'Sea of Leads' technology," MRS Bulletin, vol. 28, no. 1, pp. 61-67, Jan. 2003. (invited)

  242.  M. S. Bakir, H. D. Thacker, Z. Zhou, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of leads microwave characterization and process integration with FEOL and BEOL," in Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No. 02EX519), 2002: IEEE, pp. 116-118.

  243. A. Mule et al., "Optical waveguides with embedded air-gap cladding integrated within a sea-of-leads (SoL) wafer-level package," in Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No. 02EX519), 2002: IEEE, pp. 122-124.

  244. H. D. Thacker, M. S. Bakir, D. C. Keezer, K. P. Martin, and J. D. Meindl, "Compliant probe substrates for testing high pin-count chip scale packages," in 52nd Electronic Components and Technology Conference 2002.(Cat. No. 02CH37345), 2002: IEEE, pp. 1188-1193.

  245. M. S. Bakir, H. A. Reed, A. V. Mule, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of Leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnection," in Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No. 02CH37285), 2002: IEEE, pp. 491-494.

  246. M. S. Bakir, H. A. Reed, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of leads ultra high-density compliant wafer-level packaging technology," in 52nd Electronic Components and Technology Conference 2002.(Cat. No. 02CH37345), 2002: IEEE, pp. 1087-1094.

  247. J. D. Meindl et al., "Interconnecting device opportunities for gigascale integration (GSI)," in International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224), 2001: IEEE, pp. 23.1. 1-23.1. 4.

  248. H. A. Reed, M. S. Bakir, C. S. Patel, K. P. Martin, J. D. Meindl, and P. A. Kohl, "Compliant wafer level package (CWLP) with embedded air-gaps for sea of leads (SoL) interconnections," in Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No. 01EX461), 2001: IEEE, pp. 151-153.

  249. A. Naeemi, G. Patel, M. S. Bakir, P. Zarkesh-Ha, K. P. Martin, and J. D. Meindl, "Sea of leads: A disruptive paradigm for a system-on-a-chip (SoC)," in 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No. 01CH37177), 2001: IEEE, pp. 280-281.