Monolithic integrated circuits (ICs) have progressed at an unprecedented rate of innovation in the past 60 years. They have revolutionized every aspect of human life: communication, productivity, transportation, health, security, and manufacturing, for example. However, to meet the performance, power, and cost metrics of future electronic systems, polylithic integration has emerged as a critical enabler for the next phase of Moore’s Law. Polylithic integration enables the concatenation of heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) and materials in a manner that mimics monolithic-like densities, yet utilizes advanced off-chip ‘2.5D’ and ‘3D’ heterogeneous interconnects and packaging to provide flexibility in fabrication and design, improved scalability, improved performance and energy efficiency, reduced development time, and reduced cost. This new era of Moore’s Law is a game changer and will impact all applications, especially high-performance compute, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.

Polylithic ICs will be enabled by radical 2.5D and 3D integration architectures that require co-design and co-invention of the thermal technologies, power delivery networks, and signaling (electrical and optical) networks to unleash the ultimate performance of silicon nanoelectronic systems. Our lab, explores the co-design, fabrication, and technology demonstration of such emerging 2.5D and 3D ICs and applies these advances to emerging new applications such as machine learning and healthcare.

 

Recent News

  • $100M Investment Will Propel Absolics Inc., Georgia Tech’s Advanced Packaging Research
    December 2024
    $100M Investment Will Propel Absolics Inc., Georgia Tech’s Advanced Packaging Research
  • Semiconductor Research Corp. and Georgia Tech Secure $285M SMART USA Institute
    November 2024
    Semiconductor Research Corp. and Georgia Tech Secure $285M SMART USA Institute
  • Srujan Penta Awarded Quad Fellowship for Research on Advanced Chiplet Systems!
    November 2024
    Srujan Penta Awarded Quad Fellowship for Research on Advanced Chiplet Systems!

Recent Publications

  1. R. Krishna et al., "Yield-Aware Interposer Design for UCIe Interconnects," 2024 IEEE 33rd Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), Toronto, ON, Canada, 2024, pp. 1-3, doi: 10.1109/EPEPS61853.2024.10753661.

  2. C. -H. Kuo et al., "Selective Co ALD for Chiplet-to-Wafer and Wafer-to-Wafer Bonding," 2024 IEEE International Interconnect Technology Conference (IITC), San Jose, CA, USA, 2024, pp. 1-2, doi: 10.1109/IITC61274.2024.10732076.

  3. A. Victor and M. S. Bakir, "Tier Transfer of Ultra-thin Reconstituted-SiO2 Chiplet Tiers," in IEEE Transactions on Components, Packaging and Manufacturing Technology, doi: 10.1109/TCPMT.2025.3527427.

  4. G. Yan, E. Chung, E. Masselink, S. Oh, M, Zia, B Ramakrishnan, V. Oruganti, H. Alissa, C. Belady, Y. Im, Y. Joshi, and M. S. Bakir., "Toward TSV-Compatible Microfluidic Cooling for 3D ICs," in IEEE Transactions on Components, Packaging and Manufacturing Technology, doi: 10.1109/TCPMT.2024.3516653.  (Early Access)