Thermal PDN co-analysis

There is an exploding interest in heterogeneous integration of multi-functional chiplets into a single package using 2.5D/3D technologies, such as high-bandwidth memory with GPUs, field programmable gate arrays (FPGAs) with server processors, and high-performance GPUs with general-purpose CPUs. These high-performance integrated systems inevitably lead to higher current demand and increased power density as the power supply voltage is scaled down in recent technology nodes.  As a result, the power delivery in high-performance digital systems is an increasingly difficult challenge. Therefore, before taking full advantage of emerging 2.5-D and 3-D integration platforms, we need to first address the challenges of power delivery network (PDN) and power supply noise (PSN). PDN and PSN in traditional single-chip packages have been extensively studied in the literature. However, 2.5D and 3D integrated electronics present very unique challenges that require careful design considerations. Even more, PSN has very strong interdependence on temperature, and thus requiring thermal-PDN co-design and optimization for emerging 2.5D and 3D heterogeneous integration including back-side power delivery.

Relevant Publications

  1. A. Kaul, M. O. Hossen, M. Manley and M. S. Bakir, "Design Considerations for Power Delivery Network and Metal-Insulator-Metal Capacitor Integration in Bridge-Chips for 2.5-D Heterogeneous Integration," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 985-990.​

  2. A. Kaul, Y. Luo, X. Peng, M. Manley, Y.-C. Luo, S. Yu and M. S. Bakir, "3-D Heterogeneous Integration of RRAM-Based Compute-In-Memory: Impact of Integration Parameters on Inference Accuracy," in IEEE Transactions on Electron Devices, vol. 70, no. 2, pp. 485-492, Feb. 2023, doi: 10.1109/TED.2022.3231570.

  3. T. Zheng and M. S. Bakir, "Benchmarking Frequency-Dependent Parasitics of Fine-Pitch Off-Chip I/Os for 2.5D and 3D Heterogeneous Integration," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 12, pp. 2002-2012, Dec. 2022.

  4. M. Manley, A. Kaul, M. -J. Li and M. S. Bakir, "Ultra-Dense 3D Polylithic Integration Technology", Government Microcircuit Applications & Critical Technology Conf., Miami, FL, Mar. 2022.

  5. T. Zheng, A. Kaul, S. Kochupurackal Rajan, and M. S. Bakir, "Polylithic Integrated Circuits using 2.5D and 3D Heterogeneous Integration: Electrical and Thermal Design Considerations and Demonstrations," in B. Keser, and S. Kröhnert (Ed.), Embedded and Fan-Out Wafer and Panel Level Packaging Technologies for Advanced Application Spaces (pp. 261-287) Wiley, 2021.

  6. X. Peng, A. Kaul, M. S. Bakir and S. Yu, "Heterogeneous 3-D Integration of Multitier Compute-in-Memory Accelerators: An Electrical-Thermal Co-Design," in IEEE Transactions on Electron Devices, vol. 68, no. 11, pp. 5598-5605, Nov. 2021.

  7. Y. Hu, M. O. Hossen, Z. Wan, M.S. Bakir, and Y. Joshi, "Compact Transient Thermal Model of Microfluidically Cooled Three-Dimensional Stacked Chips With Pin-Fin Enhanced Microgap," in ASME. J. Electron. Packag., 143(3): 031007, Sep. 2021.

  8. R. Saligram, A. Kaul, M. S. Bakir, and A. Raychowdhury, “Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication,” in A. Calimera, P.-E. Gaillardon, K. Korgaonkar, S. Kvatinsky, R. Reis (Ed.), VLSI-SoC: Design Trends, (1st ed., pp. 149–178) Springer Cham, 2021.

  9. S. Kochupurackal Rajan, A. Kaul, T Sarvey, G. S. May, and M. S. Bakir, "Design Considerations, Demonstration, and Benchmarking of Silicon Micro-cold Plate and Monolithic Microfluidic Cooling for 2.5D ICs," 71st IEEE Electronic Components and Technology Conf. (ECTC),  Jun. 2021.

  10. X. Peng , W. Chakraborty, A. Kaul, W. Shim, M.S. Bakir, S. Datta, S. Yu, "Benchmarking Monolithic 3D Integration for Compute-in-Memory Accelerators: Overcoming ADC Bottlenecks and Maintaining Scalability to 7nm or Beyond," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2020.

  11. A. Kaul, X. Peng, S. Kochupurackal Rajan, S. Yu, and M.S. Bakir, "Thermal Modeling of 3D Polylithic Integration and Implications on BEOL RRAM Performance," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2020. (invited)

  12. R. Saligram, A. Kaul, A. Raychowdhury, and M.S. Bakir, "A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration," in Proc. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), virtual, Salt Lake City, UT, Oct. 2020.

  13. A. Kaul, S. Kochupurackal Rajan, M. O. Hossen, G. S. May, and M. S. Bakir, "BEOL-Embedded 3D Polylithic Integration: Thermal and Interconnection Considerations," 70th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2020.

  14. M. O. Hossen, B. Chava, G. Van der Plas, E. Beyne and M. S. Bakir, "Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and  μ TSVs," in IEEE Trans. on Electron Devices, Jan. 2020.

  15. Y. Zhang, M. O. Hossen, and M. S. Bakir, "Power delivery network modeling and benchmarking for emerging heterogeneous integration technologies," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 9, pp. 1825-1834, 2019.

  16. T. E. Sarvey, A. Kaul, S. K. Rajan, A. Dasu, R. Gutala, and M. S. Bakir, "Microfluidic Cooling of a 14-nm 2.5-D FPGA With 3-D Printed Manifolds for High-Density Computing: Design Considerations, Fabrication, and Electrical Characterization," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 9, no. 12, pp. 2393-2403, 2019.

  17. M. O. Hossen, J. L. Gonzalez, and M. S. Bakir, "Thermomechanical Analysis and Package-Level Optimization of Mechanically Flexible Interconnects for Interposer-on-Motherboard Assembly," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 8, no. 12, pp. 2081-2089, 2018.

  18. M. O. Hossen, Y. Zhang, and M. Bakir, "Thermal-Power Delivery Network Co-analysis for Multi-Die Integration", in 27th IEEE Conf. on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, Oct. 2018.

  19. Y. Zhang, M. O. Hossen, and M. S. Bakir, "Power Delivery Network Benchmarking For Interposer and Bridge-chip Based 2.5-D Integration," in IEEE Electron Device Letters, vol. 39, no. 1, pp. 99-102, Dec. 2017

  20. Y. Zhang, T. E. Sarvey, and M. S. Bakir, "Thermal evaluation of 2.5-D integration using bridge-chip technology challenges and opportunities", IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 7, no. 7, pp. 1101 - 1110, July 2017.

  21. Y. Zhang and M. S. Bakir, "Integrated thermal and power delivery network co-simulation framework for single-die and multi-die assemblies", IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 7, no. 3, pp. 434-443, Feb. 2017.

  22. Y. Zhang, X. Zhang, W. Wahby, and M. S. Bakir, "Design considerations for 2.5-D and 3-D integration accounting for thermal constraints," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Nov. 2016.

  23. D. C. Woodrum, X. Zhang, P. A. Kottke, Y. K. Joshi, A. G. Fedorov, M. S. Bakir, and S. K. Sitaraman, "Reliability assessment of hydrofoil-shaped micro-pin fins subjected to high performance coolant," in IEEE The Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  24. Y. Song, R. Abbaspour, M. S. Bakir, and S. K. Sitaraman, "Thermal annealing effects on copper microstructure in Through-Silicon-Vias," in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Las Vegas, NV, May 2016.

  25. L. Zheng, Y. Zhang, and M. Bakir, "Full-Chip Power Supply Noise Time-Domain Numerical Modeling and Analysis for Single and Stacked ICs," IEEE Transaction on Electron Devices, vol. 63, no. 3, pp. 1225-1231, Mar. 2016.

  26. W. Wahby, L. Zheng, Y. Zhang, M. S. Bakir, "A simulation tool for rapid investigation of trends in 3DIC performance and power consumption," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 6, no. 2, pp. 192-199, Feb. 2016.

  27. C. Wan, T. K. Gaylord, and M. S. Bakir, "Rigorous coupled-wave analysis equivalent-index-slab method for analyzing 3D angular misalignment in interlayer grating couplers," Applied Optics, vol. 55, no.35, pp. 10006-10015, Dec. 2016.

  28. Y. Zhang, Y. Zhang, T. E. Sarvey, C. Zhang, M. Zia, M. S. Bakir, "Thermal isolation using air gap and mechanically flexible interconnects for heterogeneous 3D ICs," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6. no. 1, pp. 31-39, Dec. 2015.

  29. X. Zhang, V. Kumar, R. Alapati, A. Naeemi and M. S. Bakir, "Interconnect performance in 3D ICs accounting TSV frequency-dependent capacitance and resistive on-chip wires: model, fabrication, and testing," in Proc. SRC Techcon, Austin, TX, Sep. 2015.

  30. L. Zheng, Y. Zhang, X. Zhang, and M. Bakir, "Silicon interposer with embedded microfluidic cooling for high-performance computing systems," in Proc. 65th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 2015.

  31. Y. Zhang, T. E. Sarvey, and M. S. Bakir, "Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Cork, Ireland, Dec. 2014.

  32. Y. Zhang, Y. Zhang, M. S. Bakir, "Thermal design and constraints for heterogeneous integrated chip stacks and isolation technology using air gap and thermal bridge," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol.4, no.12, pp.1914-1924, Dec. 2014.

  33. W. Wahby, L. Zheng, Y. Zhang, and M. Bakir, "A virtual integration platform for 3DIC design space exploration," in Proc. SRC Techcon, Austin, TX, Sep. 2014.

  34. V. Kumar, R. Sharma, E. Uzunlar, L. Zheng, R. Bashirullah, P. Kohl, M. S. Bakir, and A. Naeemi, "Airgap interconnects: modeling, optimization, and benchmarking for backplane, PCB, and interposer applications," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol.4, no.8, pp.1335-1346, Aug. 2014.

  35. P. Thadesar, L. Zheng, and M. Bakir, "Low-loss silicon interposer for three-dimensional system integration with embedded microfluidic cooling," in Proc. IEEE VLSI Technology Symposium, Honolulu, HI, June 2014.

  36. T. E. Sarvey, Y. Zhang, Y. Zhang, H. Oh, and M. S. Bakir, "Thermal and electrical effects of staggered micropin-fin dimensions for cooling of 3D microsystems,"in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Orlando, FL, May 2014.

  37. W. Wahby, A. Dembla, and M. Bakir, "Evaluation of 3DICs and fabrication of monolithic interlayer vias," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Oct. 2013.

  38. V. Kumar, L. Zheng, M. Bakir, and A. Naeemi, "Compact modeling and optimization of fine-pitch interconnects for silicon interposers", in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  39. G. Huang, M. Bakir, A. Naeemi, and J. Meindl, "Power delivery for 3-D chip stacks: physical modeling and design implication," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 2, no. 5, pp. 852-859, May 2012.

  40. L. Zheng, G. Huang, and M. Bakir, "Power delivery and thermal management for high-performance 3D chip stack," in SRC Techcon, Austin, TX, Sep. 2011.

  41. Y. Zhang, J. Zaveri, C. King, and M. Bakir, "Coupled electrical and thermal 3D IC centric microfluid heat sink design," in Proc. SRC Techcon, 2010.

  42. G. Huang, K. Shakeri, A. Naeemi, M. Bakir, and J. Meindl, "On-Chip Power Supply Noise Modeling and Chip/Package Co-Design of Gigascale and 3D Integrations," in Integrated Interconnect Technologies for 3D Nanoelectronic Systems, M. Bakir and J. Meindl (Eds.), Artech House 2009.

  43. G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. D. Meindl, “Power Delivery for 3D Chip Stacks: Physical Modeling and Design Implication,” 2007 IEEE Electrical Performance of Electronic Packaging, Oct. 2007.