Monolithic integrated circuits (ICs) have progressed at an unprecedented rate of innovation in the past 60 years. They have revolutionized every aspect of human life: communication, productivity, transportation, health, security, and manufacturing, for example. However, to meet the performance, power, and cost metrics of future electronic systems, polylithic integration has emerged as a critical enabler for the next phase of Moore’s Law. Polylithic integration enables the concatenation of heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) and materials in a manner that mimics monolithic-like densities, yet utilizes advanced off-chip ‘2.5D’ and ‘3D’ heterogeneous interconnects and packaging to provide flexibility in fabrication and design, improved scalability, improved performance and energy efficiency, reduced development time, and reduced cost. This new era of Moore’s Law is a game changer and will impact all applications, especially high-performance compute, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.

Polylithic ICs will be enabled by radical 2.5D and 3D integration architectures that require co-design and co-invention of the thermal technologies, power delivery networks, and signaling (electrical and optical) networks to unleash the ultimate performance of silicon nanoelectronic systems. Our lab, explores the co-design, fabrication, and technology demonstration of such emerging 2.5D and 3D ICs and applies these advances to emerging new applications such as machine learning and healthcare.

 

Recent News

  • I3DS Gears Up for a Promising Fall Semester
    August 2024
    I3DS Gears Up for a Promising Fall Semester
  • Bakir Named Director of the Packaging Research Center
    March 2024
    Bakir Named Director of the Packaging Research Center
  • Shengtao Yu Wins Intel Outstanding Student Paper Award at 73rd ECTC
    February 2024
    Shengtao Yu Wins Intel Outstanding Student Paper Award at 73rd ECTC

Recent Publications

  1. A. Kaul, M. Manley, J. Read, Y. Luo, X. Peng, S. Yu, M. S. Bakir, “Co-optimization for robust power delivery design in 3D-heterogeneous integration of compute-in-memory accelerators,” IEEE Symposium on VLSI Technology and Circuits (VLSI) 2024, Hawaii, USA, invited.

  2. S. Penta et al., "Performance Evaluation of UCIe-based Die-to-Die Interface on Low-Cost 2D Packaging Technology," 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), Denver, CO, USA, 2024, pp. 274-278, doi: 10.1109/ECTC51529.2024.00052. 

  3. E. Chung G. Yan, B. Ramakrishnan, H. Alissa, V. Oruganti, C. Belady, E. W. Masselink and M. S. Bakir, "Electrical-Thermal Co-analysis of TSV Embedded Microfluidic Pin-fin Heatsink for High Power Dissipation with High Bandwidth Density," 2024 IEEE 74th Electronic Components and Technology Conference (ECTC), Denver, CO, USA, 2024, pp. 1479-1484, doi: 10.1109/ECTC51529.2024.00240.

  4. E. Chung et al., "Electrical-Thermal Co-analysis of Through-Silicon Vias (TSVs) Integrated within Micropin-fin Heatsink for 3D Heterogeneous Integration (HI)," in IEEE Transactions on Components, Packaging and Manufacturing Technology, doi: 10.1109/TCPMT.2024.3452637.