CMIs

Heterogeneous integration of electronics and photonics is a promising solution to meet the high-bandwidth, low-latency, and low-energy consumption needs of modern computing systems, both for within- and off-package communication. Compared to electrical links, optical interconnects, which have many practical benefits such as high bandwidth density, low energy dissipation, and low communication latency, offer a promising solution for large-scale electronic integration. Within package photonic connectivity will be met with planar photonic links co-integrated with ultra-dense electrical interconnect network. Further, optical fibers, which offer extremely low loss, are especially critical in long-haul applications as well as in the shorter distances found in data centers and in high-performance computing (HPC). Photonic packaging, assembly, and interfacing with silicon electronics play a critical role in determining overall module performance, energy consumption, and cost. In order to create seamless polylithic integration of photonics and electronics, advances in packaging and assembly are critical. In particular, the accurate alignment and assembly of fibers or fiber arrays to a photonic integrated circuit (PIC) are crucial steps to realize high-efficiency optical packaging and integration. Moreover, the use of dense compressible microinterconnects as rematable interface between chiplets provides a number of practical benefits. The research in this thrust focuses on new photonic and electrical interconnects, fiber array alignment using microfabricated technologies, self-aligning chiplet assembly, and co-packaging of photonics and electronics. 

Relevant Publications

  1. T. Zheng and M. S. Bakir, "Electrical Demonstration of an RF Embedded Multi-Chip Module Enabled by Fused-Silica Stitch-Chip Technology," in IEEE Transactions on Components, Packaging and Manufacturing Technology, doi: 10.1109/TCPMT.2024.3395538

  2. M. Manley et al., "Towards Selective Cobalt Atomic Layer Deposition for Chip-to-Wafer 3D Heterogeneous Integration," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023, pp. 374-378.

  3. T. Zheng and M. S. Bakir, "Benchmarking and Demonstration of Low-Loss Fused-Silica Stitch-Chips with Compressible Microinterconnects for RF/mm-Wave Chiplet Based Modules," in IEEE Transactions on Components, Packaging and Manufacturing Technology.

  4. T. Zheng, M. Manley and M. Bakir, "Embedded mm-Wave Chiplet Based Module using Fused-Silica Stitch-Chip Technology: RF Characterization and Thermal Evaluation," 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, May 2023, pp. 1493-1498.

  5. S. Yu, T. K. Gaylord and M. S. Bakir, "Fiber-Array-to-Chip Interconnections With Sub-Micron Placement Accuracy via Self-Aligning Chiplets," in IEEE Photonics Technology Letters, vol. 34, no. 19, pp. 1023-1025, 1 Oct. 2022.

  6. T. Zheng and M. S. Bakir, “Fused-Silica Stitch-Chips with Compressible Microinterconnects for Embedded RF/mm-wave Chiplets”, in 2022 IEEE/MTT-S International Microwave Symposium (IMS), Denver, CO, Jun. 2022.

  7. Z. J. Devereaux, M. Manley, M.-J. Li, J. Hollin, N. M. K. Linn, M. S. Bakir, A. Kummel and C. H. Winter, “Studies Toward Highly Selective Cobalt Metal ALD on Copper Features for Heterogeneous Chiplet Integration”, 6th Area Selective Deposition Workshop, San Francisco, CA, Apr. 2022.​

  8. J. R. Brescia, J. L. Gonzalez, T. Zheng and M. S. Bakir, "Replaceable Integrated Chiplet (PINCH) Assembly for Heterogeneous Integration", Government Microcircuit Applications & Critical Technology Conf., Miami, FL, Mar. 2022.

  9. M. -J. Li and M. S. Bakir, "3-D Integrated Chiplet Encapsulation (3-D ICE): High-Density Heterogeneous Integration Using SiO2-Reconstituted Tiers," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 12, pp. 2242-2245, Dec. 2021.

  10. J. L. Gonzalez, J. R. Brescia, T. Zheng, S. Kochupurackal Rajan and M. S. Bakir, "A Die-Level, Replaceable Integrated Chiplet (PINCH) Assembly Using a Socketed Platform, Compressible MicroInterconnects, and Self-Alignment," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 12, pp. 2069-2076, Dec. 2021.

  11. T. Zheng, P. K. Jo, S. Kochupurackal Rajan and M. S. Bakir, "Electrical Characterization and Benchmarking of Polylithic Integration Using Fused-Silica Stitch-Chips With Compressible Microinterconnects for RF/mm-Wave Applications," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 11, pp. 1824-1834, Nov. 2021.

  12. Y. Wang, C. Swank, T. Zheng, J. F. Buckwalter, A. Kummel, M. Rodwell and M. S. Bakir, “Interposer and Advanced Packaging Enabled by Ultra-Dense Microdiamond Composites for RF/mm-wave Applications”, in Proceeding of TECHCON 2021, Sep. 2021.

  13. M. -J. Li et al., "Cu–Cu Bonding Using Selective Cobalt Atomic Layer Deposition for 2.5-D/3-D Chip Integration Technologies," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 12, pp. 2125-2128, Dec. 2020.

  14. R. Saligram, A. Kaul, A. Raychowdhury, and M.S. Bakir, "A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration," in Proc. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), virtual, Salt Lake City, UT, Oct. 2020.

  15. P. Jo, S. Kochupurackal Rajan, J. Gonzalez and M. S. Bakir, "Polylithic Integration of 2.5-D and 3-D Chiplets Enabled by Multi-Height and Fine-Pitch CMIs,"  in IEEE Transactions on Components, Packaging and Manufacturing Technology, Jul.2020.

  16. H. Oh, M. Swaminathan, G. S. May and M. S. Bakir, "Electrical Circuit Modeling and Validation of Through-Silicon Vias Embedded in a Silicon Microfluidic Pin-Fin Heat Sink Filled With Deionized Water," in IEEE Trans. on Comp., Pack. and Manuf. Tech., Aug. 2020.

  17. T. Zheng, P. K. Jo, S. Kochupurackal Rajan, and M. S. Bakir, "Polylithic integration for RF/mm-wave chiplets using stitch-chips: modeling, fabrication, and characterization," 2020 IEEE MTT-S International Microwave Symposium (IMS), Los Angeles, CA, Jun. 2020.

  18. A. Kaul, S. Kochupurackal Rajan, M. O. Hossen, G. S. May, and M. S. Bakir, "BEOL-Embedded 3D Polylithic Integration: Thermal and Interconnection Considerations," 70th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2020.

  19. J. L. Gonzalez, T. Zheng, S. Kochupurackal Rajan, and M. S. Bakir, “Package Testing using a Socketed Heterogeneous 2.5D/3D Integration Module (SHIM) for mm-wave Applications,” Proceedings of the 2020 GOMAC-Tech – Government Microcircuit Applications and Critical Technology Conference, 2020.

  20. M. O. Hossen, B. Chava, G. Van der Plas, E. Beyne and M. S. Bakir, "Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and  μ TSVs," in IEEE Trans. on Electron Devices, Jan. 2020.

  21. S. Kochupurackal Rajan, M. Li, G.S. May, and M.S. Bakir, "High density and low-temperature interconnection enabled by mechanical self-alignment and electroless plating" in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Sendai, Japan, Oct. 2019.

  22. C. Wan, J. L. Gonzalez, T. Fan, A. Adibi, T. K. Gaylord, and M. S. Bakir, "Fiber-Interconnect Silicon Chiplet Technology for Self-Aligned Fiber-to-Chip Assembly," IEEE Photonics Technology Letters, vol. 31, no. 16, pp. 1311-1314, 2019.

  23. P. K. Jo, T. Zheng, and M. S. Bakir, "Polylithic Integration of 2.5D and 3D Chiplets Using Interconnect Stitching," in Proc. 69th IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May. 2019.

  24. M. Zia, B. Chung, S. J. Sober and M.S. Bakir, "Fabrication and Characterization of 3D Multi-Electrode Array on Flexible Substrate for In Vivo EMG Recording from Expiratory Muscle of Songbird," in Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2018.

  25. P. K. Jo, T. Zheng, and M. S. Bakir, "Multi-Die Polylithic Integration Enabled by Heterogeneous Interconnect Stitching Technology (HIST)," in 27th IEEE Conf. on Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, Oct. 2018.

  26. P. K. Jo, M. O. Hossen, X. Zhang, Y. Zhang, and M. S. Bakir, "Heterogeneous Multi-Die Stitching: Technology Demonstration and Design Considerations," in Proc. 68th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May. 2018.

  27. C. Wan, T. K. Gaylord, and M. S. Bakir, "Grating-assisted-cylindrical-resonant-cavities interlayer coupler," Applied Optics, vol. 57, no. 18, pp. 5079-5089, June 2018.

  28.  P. Yeon, J. L. Gonzalez, M. Zia, S. Kochupurackal Rajan, G. S. May, M. S. Bakir, and M. Ghovanloo, "Microfabrication, Assembly, and Hermetic Packaging of mm-Sized Free-Floating Neural Probes," in Proc. IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, Oct. 2017.

  29.  P. K. Jo, M. Zia, J. L. Gonzalez, and M. S. Bakir, "Dense and highly elastic compressible microinterconnects (CMIs) for electronic microsystems," in Proc. 67th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May. 2017.

  30.  H. Oh, X. Zhang, P. K. Jo, G. S. May, and M. S. Bakir, "Monolithic-like heterogeneously integrated microsystems using dense low-loss interconnects," in Proc. IEEE Silicon Monolithic Integrated Circuits in RF Systems (SiRF), Phoenix, AZ, Jan. 2017. (invited).

  31. C. Wan, T. K. Gaylord, and M. S. Bakir, "Circular waveguide grating-via-grating for interlayer coupling," IEEE Photonics Technology Letters, vol. 29, no. 21, pp. 1776-1779, Nov. 2017.

  32. M.Zia, C.Wan, Y. Zhang and M.S. Bakir, “Electrical and photonic off-chip interconnection and system integration,” in Tolga Tekin, Nikos Pleros, Richard Pitwon, and Andreas Hakansson (Ed.), “Optical Interconnects for Data Centers,” (1st Edition p.265-286), Woodhead Publishing, Nov. 2016

  33.  C. Wan, T. K. Gaylord, and M. S. Bakir, "Grating design for 3-D interconnections of waveguides in overlaid chips using the RCWA-EIS method," in Frontiers in Optics, Rochester, NY, Oct. 2016.

  34. M. Zia, C. Zhang, H.S. Yang, L. Zheng and Muhannad Bakir, "Chip-to-chip interconnect integration technologies," IEICE Electron. Express, vol. 13, no. 6, pp. 1-16, Mar. 2016.

  35. H. Oh, P. A. Thadesar, G. S. May, and M. S. Bakir, "Low-Loss Air-Isolated Through-Silicon Vias for Silicon Interposers," IEEE Microw. Wirel. Components Lett., vol. 26, no. 3, pp. 168-170, Mar. 2016.

  36. H. Oh, G. May, and M. Bakir, "Analysis of signal propagation through TSVs within distilled water for liquid-cooled microsystems," IEEE Transaction Electron Devices, vol. 63, no. 3, pp. 1176-1181, Mar. 2016.

  37. X. Zhang, X. Han, T. E. Sarvey, C. E. Green, P. A. Kottke, A. G. Fedorov, Y. Joshi, and M. S. Bakir, "3D IC with embedded microfluidic cooling technology, thermal performance, and electrical implications," ASME Journal of Electronic Packaging, vol. 138, pp. 1-6, Mar. 2016.

  38. P. Thadesar and M. S. Bakir, "Fabrication and characterization of polymer-enhanced TSVs, inductors and antennas for mixed-signal silicon interposer platforms," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 6, no. 3, pp. 455-463, Mar. 2016.

  39. C. Wan, T. K. Gaylord, and M. S. Bakir, "Grating design for interlayer optical interconnection of in-plane waveguides," Applied Optics, vol. 55, no.10, pp. 2601-2610, Oct. 2016.

  40. C. Wan, T. K. Gaylord, and M. S. Bakir, "RCWA-EIS method for interlayer grating coupling," Applied Optics, vol. 55, no. 22, pp. 5900-5908, Aug. 2016.

  41. H. Oh, Y. Zhang, L. Zheng, G. S. May, and M. S. Bakir, "Fabrication and characterization of electrical interconnects and microfluidic cooling for 3D ICs with silicon interposer," Heat Transf. Eng., vol. 7632, pp. 1-41, Dec. 2015 (Invited).

  42. X. Zhang, V. Kumar, R. Alapati, A. Naeemi and M. S. Bakir, "Interconnect performance in 3D ICs accounting TSV frequency-dependent capacitance and resistive on-chip wires: model, fabrication, and testing," in Proc. SRC Techcon, Austin, TX, Sep. 2015.

  43. H. Oh, J. M. Gu, S. J. Hong, G. S. May, and M. S. Bakir, "High-aspect ratio through-silicon vias for the integration of microfluidic cooling with 3D microsystems," Microelectronic Engineering, vol. 142, pp. 30-35, July 2015.

  44. P. Thadesar and M. Bakir, "Fabrication and characterization of mixed-signal polymer-enhanced silicon interposer featuring photodefined coax TSVs and high-Q inductors," in Proc. 65th IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, May 2015.

  45. C. Zhang, P. Thadesar, M. Zia, T. E. Sarvey, and M. S. Bakir, "Au-NiW mechanically flexible interconnects (MFIs) for rematable 3D integration," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), Cork, Ireland, Dec. 2014.

  46. H. S. Yang, C. Zhang, and M. Bakir, "Self-aligned silicon interposer tiles and silicon bridges using positive self-alignment structures and rematable mechanically flexible interconnects", IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 4, no. 11, pp. 1760-1768, Nov. 2014.

  47. W. Wahby, L. Zheng, Y. Zhang, and M. Bakir, "A virtual integration platform for 3DIC design space exploration," in Proc. SRC Techcon, Austin, TX, Sep. 2014.

  48. X. Liu, P. Thadesar, C. Taylor, H. Oh, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "In-situ microscale through-silicon via strain measurements by synchrotron x-ray microdiffraction exploring the physics behind data interpretation," Applied Physics Letters, vol.105, no.11, p.112109, Sep. 2014.

  49. H. Oh, Y. Zhang, L. Zheng, and M. Bakir,"Electrical interconnect and microfluidic cooling within 3D ICs and silicon interposer," in Proc. Int. Tech. Conf. and Expo. Packaging and Integration of Electronic and Photonic Microsystems and Int. Conf. Nanochannels, Microchannels, and Minichannels (InterPACKICNMM), Chicago, IL, Aug. 2014.

  50. V. Kumar, R. Sharma, E. Uzunlar, L. Zheng, R. Bashirullah, P. Kohl, M. S. Bakir, and A. Naeemi, "Airgap interconnects: modeling, optimization, and benchmarking for backplane, PCB, and interposer applications," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol.4, no.8, pp.1335-1346, Aug. 2014.

  51. J. M. Gu, P. Thadesar, A. Dembla, M. S. Bakir, G. S. May, and S. J. Hong "Endpoint detection in low open area TSV fabrication using optical emission spectroscopy," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 4, no. 7, pp. 1251-1260, July 2014.

  52. P. Thadesar, L. Zheng, and M. Bakir, "Low-loss silicon interposer for three-dimensional system integration with embedded microfluidic cooling," in Proc. IEEE VLSI Technology Symposium, Honolulu, HI, June 2014.

  53. C. Zhang, H.S. Yang, M. Bakir, "Mechanically flexible interconnects with highly scalable pitch and large stand-off height for silicon interposer tile and bridge interconnection," in Proc. 64th IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2014.

  54. H. S. Yang, C. Zhang, M. Zia, L. Zheng, M. Bakir, "Interposer-to-interposer electrical and silicon photonic interconnection platform using silicon bridge," in Proc. IEEE Photonics Society Optical Interconnects Conf., Coronado, CA, May 2014.

  55. T. E. Sarvey, Y. Zhang, Y. Zhang, H. Oh, and M. S. Bakir, "Thermal and electrical effects of staggered micropin-fin dimensions for cooling of 3D microsystems,"in IEEE Intersociety Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM), Orlando, FL, May 2014.

  56. C. Zhang, H. S. Yang, and M. Bakir, "Mechanically flexible interconnects (MFIs) with highly scalable pitch," Journal of Micromechanics and Microengineering, vol. 24, no. 5, pp. 055024, May 2014.

  57. W. Wahby, A. Dembla, and M. Bakir, "Evaluation of 3DICs and fabrication of monolithic interlayer vias," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Oct. 2013.

  58. Y. Zhang, H. Oh, and M. Bakir, "Within-tier cooling and thermal isolation technologies for heterogeneous 3D ICs," in Proc. IEEE Int. 3D Systems Integration Conf. (3DIC), San Francisco, CA, Oct. 2013.

  59. C. Zhang, H. S. Yang, and M. Bakir, "Highly elastic gold passivated mechanically flexible interconnects," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 3, no. 10, pp. 1632-1639, Oct. 2013.

  60. H. Oh, A. Dembla, Y. Zhang, and M. Bakir "High aspect ratio TSVs in micro-pinfin heat sinks for 3D ICs," in Proc. SRC TECHCON, Austin, TX, Sep. 2013.

  61. Best in Session Paper Award: P. Thadesar and M. Bakir "Fabrication and wideband characterization of novel photodefined polymer-embedded vias for silicon interposers," in Proc. SRC TECHCON, Austin, TX, Sep. 2013.

  62. X. Liu, P. Thadesar, C. Taylor, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "Dimension and liner dependent thermomechanical strain characterization of through-silicon vias using synchrotron x-ray diffraction," Journal of Applied Physics, vol. 114, no. 6, pp. 064908, Aug. 2013.

  63. P. Thadesar and M. Bakir, "Novel photo-defined polymer-enhanced through-silicon vias for silicon interposers," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol. 3, no. 7, pp. 1130-1137, July 2013.

  64. X. Liu, P. Thadesar, C. Taylor, M. Kunz, N. Tamura, M. Bakir, and S. Sitaraman, "Thermomechanical strain measurements by synchrotron x-ray diffraction and data interpretation for through-silicon vias," Applied Physics Letters , vol. 103, no. 2, pp. 022107-1-022107-5, July 2013.

  65. P. Thadesar, A. Dembla, D. Brown, and M. S. Bakir, "Novel through-silicon via technologies for 3D system integration," in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  66. J. M. Gu, P. Thadesar, A. Dembla, S. J. Hong, M. S. Bakir, and G. May, "Endpoint detection using optical emission spectroscopy in TSV fabrication," in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  67. V. Kumar, L. Zheng, M. Bakir, and A. Naeemi, "Compact modeling and optimization of fine-pitch interconnects for silicon interposers", in Proc. IEEE International Interconnect Technology Conf. (IITC), Kyoto, Japan, June 2013.

  68. P. Thadesar, J. M. Gu, A. Dembla, S. J. Hong, G. S. May and M. S. Bakir, "Novel photodefined polymer-clad through-silicon via technology integrated with end point detection using optical emission spectroscopy," in Proc. 24th Annual SEMI Advanced Semiconductor Manufacturing Conf. (ASMC), Saratoga Springs, NY, May 2013.

  69. L. Zheng, Y. Zhang and M. Bakir, "Design, fabrication and assembly of novel electrical and microfluidic I/Os for 3-D chip stack and silicon interposer," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.

  70. P. Thadesar and M. Bakir, "Fabrication and characterization of novel photodefined polymer-enhanced through-silicon vias for silicon interposers," in Proc. 63rd IEEE Electronic Components and Technology Conf. (ECTC), Las Vegas, NV, May 2013.

  71. H. S. Yang, P. Thadesar, C. Zhang, M.S. Bakir, (2013). Mechanically Flexible Interconnects and TSVs: Applications in CMOS/MEMS Integration. In L. A. Francis and K. Iniewski (Ed.), Novel Advances in Microsystems Technologies and Their Applications (1st ed., p45-p68). FL, USA: CRC Press

  72. P. Thadesar and M. Bakir, "Novel low-loss photodefined electrical TSVs for silicon interposers," Topical Workshop on Advanced 3D Packaging, 9th IMAPS Int. Conf. and Exhibition on Device Packaging, Scottsdale/Fountain Hills, AZ, Mar. 2013.

  73. P. Thadesar and M. Bakir, "Novel photodefined polymer-embedded vias for silicon interposers," Journal of Micromechanics and Microengineering, vol. 23, no. 3, pp. 035003-1-035003-6, Mar. 2013.

  74. H. S. Yang, P. Thadesar, C. Zhang, M.S. Bakir, (2013). Mechanically Flexible Interconnects and TSVs: Applications in CMOS/MEMS Integration. In V. Choudhary and K. Iniewski (Ed.), MEMS: Fundamental Technology and Applications (1st ed., p111-p130). FL, USA: CRC Press

  75. P. Thadesar and M. Bakir, "Silicon interposer featuring novel electrical and optical TSVs," in Proc. ASME International Mechanical Engineering Congress and Exposition, Houston, TX, Nov. 2012.

  76. A. Dembla, Y. Zhang, and M. Bakir, "Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs," in Proc. SRC TECHCON, Austin, TX, Sep. 2012.

  77. L. Zheng and M. Bakir, "Electrical and fluidic microbumps and interconnects for 3D-IC and silicon interposer," in Proc. IEEE International System-on-Chip Conf. (SoCC), 2012.

  78. A. Dembla, Y. Zhang, and M. Bakir, "High aspect ratio TSVs in micropin-fin heat sinks for 3D ICs," in Proc. IEEE Int. Conf. Nanotechnology, Birmingham, England, Aug. 2012.

  79. A. Dembla, Y. Zhang, and M. Bakir, "Fine pitch TSV integration in silicon micropin-fin heat sinks for 3D ICs," in Proc. IEEE International Interconnect Technology Conf. (IITC), San Jose, CA, June 2012.

  80. C. Zhang, H. S. Yang, and M. Bakir, "Gold passivated mechanically flexible interconnects (MFIs) with high elastic deformation," in Proc. 62nd IEEE Electronic Components and Technology Conf. (ECTC), San Diego, CA, 2012.

  81. H. S. Yang, M. S. Bakir, "Design, fabrication, and characterization of freestanding mechanically flexible interconnects using curved sacrificial layer," IEEE Transaction on Components, Packaging and Manufacturing Technology, vol.2, no.4, pp.561-568, Apr. 2012

  82. H. S. Yang, R. Ravindran, C. Zhang, P. Modarres, and M. Bakir, "Enabling technologies for 3D stacking of disposable electronic biosensor and CMOS Chips," Future Fab International, pp. 80-85, Oct. 2011. (invited)

  83. A. Dembla, D. Brown, and M. Bakir, "Nanofabrication of ultra high density nanoscale TSVs," in SRC Techcon, Austin, TX, Sep. 2011.

  84. H. S. Yang and M. Bakir, "Design and wafer-level fabrication of positive self-alignment structures for improved vertical optical coupling," in IMAPS/IEEE-CPMT Advanced Technology Workshop on Optoelectronic Packaging, Irvine, CA, June 2011.

  85. Y. Zhang, C. King, J. Zaveri, Y. J. Kim, V. Sahu, Y. Joshi, and M. Bakir, "Coupled electrical and thermal 3D IC centric microfluidic heat sink design and technology," in Proc. 61st IEEE Electronic Components and Technology Conf. (ECTC), Orlando, FL, May 2011.

  86. M. Parekh, P. Thadesar and M. Bakir, "Electrical, optical, and fluidic through-silicon vias for silicon interposer applications," in Proc. 61st IEEE Electronic Components and Technology Conf., Lake Buena Vista, FL, May 2011.

  87. A. Dembla, D. Brown, and M. Bakir, "Nanofabrication of high aspect ratio nanoscale TSVs," in Proc. Electron, Ion, and Photon Beam Technology and Nanofabrication (EIPBN), Las Vegas, NV, May. 2011.

  88. M. Bakir, P. Thadesar, C. King, J. Zaveri, H. Yang, C. Zhang, Y. Zhang, "Revolutionary innovation in system interconnection: A new era for the IC," in Proc. Photonics West, Proc. of SPIE, Feb. 2011.

  89. H. S. Yang and M. Bakir, "3D integration of CMOS and MEMS using MFI and TSV," in Proc. SRC Techcon, 2010.

  90. C. King, J. Zaveri, M. Bakir, and J. Meindl, "Electrical and fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs," in Proc. IEEE Electronic Components and Technology Conf., pp. 822-828, 2010.

  91. H. S. Yang and M. Bakir, "3D integration of CMOS and MEMS using mechanically flexible interconnects (MFI) and through silicon vias (TSV)," in Proc. IEEE Electronic Components and Technol. Conf., pp. 822-828, 2010.

  92. H. S. Yang, R. Ravindran, M. S. Bakir, J.D. Meindl, "A 3D interconnect system for large biosensor array and CMOS signal-processing IC integration," IEEE Interconnect Technology Conf. (IITC), 2010 International, 6-9 June 2010

  93. H. S. Yang and M. Bakir, "Interconnect technologies for 3D integration of CMOS and MEMS," in Proc. MRS Spring Meeting, 2010. (invited)

  94. J.-H Lai, H. S. Yang, H. Chen, C. King, J. Zaveri, R. Ravindran, and M. Bakir, "A 'mesh' seed layer for improved through-silicon-via fabrication," Journal of Micromechanics and Microengineering, vol. 20, no. 2, pp. 025016-1-025016-6, Jan. 2010.

  95. J. Zaveri, C. King Jr., H.S. Yang, M.S. Bakir, "Wafer level batch fabrication of silicon microchannel heat sinks and electrical through silicon vias for 3D ICs," IMAPS 42nd International Symposium on Microelectronics, 2009.

  96. J. Zaveri, C. King, H. Yang, and M. Bakir, "Wafer level batch fabrication of silicon microchannel heat sinks and electrical through silicon vias" in Proc. SRC TECHCON, 2009.

  97. C. King, J. Zaveri, H. S. Yang, M. Bakir, and J. Meindl "Electro-fluidic C4 interconnections for inter-layer liquid cooling of 3D ICs," in Proc. SRC TECHCON, 2009.

  98. M. Bakir and J. Meindl (Eds.), "Integrated Interconnect Technologies for 3D Nanoelectronic Systems", Artech House, 2009. (16 chapters; 550-pages)

  99. M. S. Bakir, C. King, D. Sekar, H. Thacker, B. Dang, G. Huang, A. Naeemi, and J. D. Meindl, “3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation,” 2008 IEEE Custom Integrated Circuits Conference, Sep. 2008.

  100. C. King, D. Sekar, M. Bakir, B. Dang, J. Pikarsky, and J. Meindl, "3D stacking of chips with electrical and microfluidic I/O interconnects," in Proc. SRC TECHCON, 2008.

  101. M. Bakir, A. Glebov, M. Lee, P. Kohl, and J. Meindl, "Mechanically flexible chip-to-substrate optical interconnections using optical pillars," IEEE Transaction on Adv. Packaging, vol. 31, no. 1, pp. 143-153, Feb. 2008.

  102. M. S. Bakir, B. Dang, and J. D. Meindl, “Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems,” 2007 IEEE Custom Integrated Circuits Conference, Sep. 2007.

  103. M. Bakir, B. Dang, O. Ogunsola, R. Sarvari, and J. Meindl, "Electrical and optical chip I/O interconnections for gigascale systems," IEEE Transaction on Electron Devices, vol. 54, no. 9, pp. 2426-2437, Sep. 2007.

  104. M. S. Bakir, B. Dang, and J. D. Meindl, “Electrical, Optical and Thermofluidic Chip I/O Interconnections,” ASME 2007 InterPACK Conference, Volume 1, Jul. 2007.

  105. M. Bakir and J. Meindl, "Fully compatible low cost electrical, optical, and fluidic I/O interconnect networks for ultimate performance 3D gigascale systems," in Proc. Int. 3D System-in-Chip Conf., 2007. (invited, Tokyo,  Japan)

  106. M. S. Bakir, B. Dang, O. O. Ogunsola, and J. D. Meindl, “‘trimoda’ Wafer-Level Package: Fully Compatible Electrical, Optical, and Fluidic Chip I/O Interconnects,” 2007 Proceedings 57th Electronic Components and Technology Conference, May 2007.

  107. M. S. Bakir, P. A. Kohl, A. L. Glebov, E. Elce, D. Bhusari, M. G. Lee, and J. D. Meindl, “Flexible polymer pillars for optical chip assembly: materials, structures, and characterization,” Photonics Packaging, Integration, and Interconnects VII, Feb. 2007.

  108. M. Bakir, "Nanoimprint Lithography for Semiconductor and Interconnect Technologies," in NanoTechnology: An Open Text, S. Campbell (Ed.), NSF NNIN 2007.

  109. H. Thacker, O. Ogunsola, A. Carson, M. Bakir, and J. Meindl, “Optical Through-Wafer Interconnects for 3D Hyper-Integration,” LEOS 2006 - 19th Annual Meeting of the IEEE Lasers and Electro-Optics Society, Oct. 2006.

  110. O. Ogunsola, H. D. Thacker, B. L. Bachim, M. S. Bakir, J. Pikarsky, T. K. Gaylord, and J. D. Meindl, "Chip-level waveguide-mirror-pillar optical interconnect structure," IEEE Photon. Technol. Lett., vol. 18, no. 15, pp. 1672-1674, Aug. 2006.

  111. K.-N. Chen, M. Bakir, J. Meindl, and R. Reif, "Copper interconnect bonding for polymer pillar I/O interconnects and three-dimensional (3D) integration applications," in Proc. TMS Electronics Materials Conf., 2006.

  112. B. Dang, M. S. Bakir, C. S. Patel, H. D. Thacker, and J. D. Meindl, "Sea-of-Leads MEMS I/O interconnects for low-k IC packaging," IEEE J. Microelectromechanical Systems, vol. 15, no. 3, pp. 523-530, June 2006.

  113. O. Ogunsola, H. Thacker, B. Bachim, M. Bakir, T. Gaylord, and J. Meindl, “Polymer Pillars as Optical I/O for Gigascale Chips using Mirror-Terminated Waveguides,” 2006 International Interconnect Technology Conference, Jun. 2006.

  114. M. S. Bakir, B. Dang, H. D. Thacker, O. O. Ogunsola, R. Ogra, and J. Meindl, “Dual-Mode Electrical-Optical Flip-Chip I/O Interconnects and a Compatible Probe Substrate for Wafer-Level Testing,” 56th Electronic Components and Technology Conference 2006, May 2006.

  115. A. He, M. S. Bakir, S. Ann, B. Allen, and P. Kohl, “Fabrication of Compliant, Copper-Based Chip-to-Substrate Connections,” 56th Electronic Components and Technology Conference 2006, May 2006.

  116. L. Glebov, D. Bhusari, P. Kohl, M. Bakir, J. Meindl, and M. G. Lee, "Flexible pillars for displacement compensation in optical chip assembly," IEEE. Photon. Technol. Lett., vol. 18, no. 6, pp. 974-976, Apr. 2006.

  117. B. Dang, M. S. Bakir, and J. D. Meindl, "Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink," IEEE Electron Device Letters, vol. 27, no. 2, pp. 117-119, Feb. 2006.

  118. M. S. Bakir, B. Dang, R. Emery, G. Vandentop, P. A. Kohl, and J. D. Meindl, "Sea of Leads compliant I/O interconnection process integration for the ultimate enabling of chips with low-k interlayer dielectrics," IEEE J. Adv. Packag., vol. 28, no. 3, pp. 488-494, Aug. 2005.

  119. H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, “Probe Module for Wafer-Level Testing of Gigascale Chips With Electrical and Optical I/O Interconnects,” Advances in Electronic Packaging, Parts A, B, and C, Jul. 2005.

  120. B. Dang, P. J. Joseph, X. Wei, M. S. Bakir, P. A. Kohl, Y. K. Joshi, and J. D. Meindl, “A Chip-Scale Cooling Scheme With Integrated Heat Sink and Thermal-Fluidic I/O Interconnects,” in Proc. ASME InterPACK, Jul. 2005.

  121. H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, “High-density probe substrate for testing optical interconnects,” Proceedings of the IEEE 2005 International Interconnect Technology Conference, Jun. 2005.

  122. H. Thacker, O. Ogunsola, M. Bakir, and J. Meindl, "Probe module for wafer-level testing of gigascale chips with polymer pillar-based electrical and optical I/O interconnects," in Proc. SRC TECHCON, 2005.

  123. O. Ogunsola, H. Thacker, B. Bachim, M. Bakir, T. Gaylord, J. Meindl, "Mirror-enabled polymer pillar optical I/O interconnects for gigascale integration," in Proc. SRC TECHCON, 2005.

  124. M. Bakir, and J. D. Meindl, "Wafer-level packaging of optoelectronic chips using sea of leads electrical and optical I/O interconnections," in The 17th Annual Meeting of the IEEELasers and Electro-Optics Society, 2004: IEEE, pp. 583-584.

  125. M. S. Bakir and J. D. Meindl, "Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration," IEEE Transaction Electron Devices, vol. 51, no. 7, pp. 1069-1077, July 2004.

  126. M. S. Bakir, C. O. Chui, A. K. Okyay, K. C. Saraswat, and J. D. Meindl, "Integration of optical polymer pillars chip I/O interconnections with Si MSM photodetectors," IEEE Transaction on Electron Devices, vol. 51, no. 7, pp. 1084-1090, July 2004.

  127. M. S. Bakir, T. K. Gaylord, O. O. Ogunsola, E. G. Glytsis, and J. D. Meindl, "Optical transmission of polymer pillars for chip I/O optical interconnections," IEEE Photon. Technol. Lett., vol. 16, no. 1, pp. 117-119, Jan. 2004.

  128. M. S. Bakir, T. K. Gaylord, K. P. Martin, and J. D. Meindl, "Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections," IEEE Photon. Technol. Lett., vol. 15, no. 11, pp. 1567-1569, Nov. 2003.

  129. D. C. Keezer, C. S. Patel, M. S. Bakir, Q. Zhou, and J. D. Meindl, "Electrical test strategies for a wafer-level packaging technology," IEEE Trans. Electron. Packag. Manufac., vol. 26, no. 4, pp. 267-272, Oct. 2003.

  130. M. S. Bakir, H. A. Reed, H. D. Thacker, P. A. Kohl, K. P. Martin, and J. D. Meindl, "Sea of leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)," IEEE Trans. Electron Devices, vol. 50, no. 10, pp. 2039-2048, Oct. 2003.

  131. M. S. Bakir, T. Gaylord, P. Kohl, K. Martin, and J. Meindl, "Sea of dual mode polymer pillar I/O interconnections for gigascale integration," in 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC., 2003: IEEE, pp. 372-373.

  132. M. S. Bakir, H. A. Reed, A. V. Mule, J. Jayachandran, P. A. Kohl, T. K. Gaylord, K. P. Martin, and J. D. Meindl, "Chip-to-module interconnections using 'Sea of Leads' technology," MRS Bulletin, vol. 28, no. 1, pp. 61-67, Jan. 2003. (invited)

  133. A. Mule et al., "Optical waveguides with embedded air-gap cladding integrated within a sea-of-leads (SoL) wafer-level package," in Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No. 02EX519), 2002: IEEE, pp. 122-124.